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- A Remote Verification Framework to Assess the Robustness of Circuits to Soft FaultsPublication . Alves, Gustavo R.; Gericota, Manuel G.; Fidalgo, André VazThe growing number of circuits implemented in Field Programmable Gate Arrays (FPGAs) and the increased susceptibility, due to higher integration levels, of these devices to soft faults caused by radiation at ground level is leading the scientific and technical community to the study of new fault tolerant designs and solutions, and how they can be verified and validated. Using fault injection techniques and enhanced debug tools to inject faults in a circuit and observing its behaviour in the presence of such faults, respectively, is a proven solution for the previous verification and validation problem. This paper presents the underlying concepts for a remote verification framework to assess the robustness of circuits to soft faults. It comprises a verification platform and a set of verification services that can be used in a remote or local fashions.
- An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsThe use of partial and dynamically reconfigurable FPGAs in reconfigurable systems opens exciting possibilities, since they enable the concurrent reconfiguration of part of the system without interrupting its operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of failures after many reconfiguration processes. New methods of test and fault tolerance are therefore required, capable of ensuring system reliability. This paper presents improvements to our RaT Freed Resources technique, originally present in [1], a structural concurrent test approach able to detect and diagnosis faults without disturbing system operation, throughout its lifetime.
- DRAFT: A Scanning Test Methodology for Dynamic and Partially Reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsA new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the IEEE 1149.1 Boundary Scan test infrastructure, already widely employed for In-System Programming.
- Testando ...Publication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsOs dispositivos lógicos reconfiguráveis, nomeadamente as FPGAs (Field Programmable Gate Arrays), conheceram uma considerável expansão nos últimos anos. A utilização deste tipo de componentes permite uma poupança de espaço nas placas de circuito impresso e uma mais rápida transição do projecto para o mercado, com um nível inigualável de flexibilidade quando comparado com a tradicional lógica discreta com funcionalidade pré-definida. Estas vantagens foram reforçadas pelo recente aparecimento de FPGAs dinâmica e parcialmente reconfiguráveis (de que a família Virtex da Xilinx é um exemplo), as quais permitem a adaptação dinâmica das funções implementadas pelo hardware a uma aplicação ou a um sistema em particular, sem interromper o funcionamento de todo o sistema, isto é, a funcionalidade destes dispositivos pode ser modificada sem que tal implique a sua paragem ou a do sistema em que se encontram inseridos. Esta nova possibilidade levanta, no entanto, uma questão: como garantir que, independentemente da funcionalidade implementada após múltiplos processos de reconfiguração, o sistema continua a operar sem falhas? Este trabalho procura dar resposta a esta questão propondo um novo método de teste estrutural concorrente, baseado no princípio da replicação e libertação de recursos para serem testados.
- On-line Testing of FPGA Logic Blocks Using Active ReplicationPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, José M.This paper presents a novel on-line test method for partial and dynamically reconfigurable FPGAs, based on the active replication of configurable logic blocks (CLBs). Each CLB in the FPGA is released for test and again made available to be reused if fault-free, or removed from operation if faulty. The proposed method continuously scans the whole FPGA without disturbing system operation. It implies a very low overhead at chip level, since all the test actions are carried out through the IEEE 1149.1 standard boundary-scan architecture and test access port. Moreover, it presents the additional benefit of correcting transient faults, such as single event upsets in space environments, which would otherwise become permanent faults and most likely introduce functional restrictions or even halt the system.
- The RAT technique for concurrent test of dynamically reconfigurable hardwarePublication . Gericota, Manuel G.; Alves, Gustavo R.; Ferreira, J. M. MartinsA new class of FPGAs that enable partial and dynamic reconfiguration has been recently introduced into the market, opening exciting possibilities for dynamically reconfigurable hardware systems. While enabling concurrent reconfiguration without disturbing system operation, this technology also raises a new test challenge: the reconfiguration process can activate faults which would otherwise not be visible. This paper proposes a structural concurrent test method that reuses the IEEE 1149.1 infrastructure, exploiting the same dynamic and partially reconfigurable features underlying this test challenge.
- FPGA Architectures for Reconfigurable ComputingPublication . Gericota, Manuel G.; Alves, Gustavo R.; Ferreira, J. M.To accelerate the execution of an application, repetitive logic and arithmetic computation tasks may be mapped to reconfigurable hardware, since dedicated hardware can deliver much higher speeds than those of a general-purpose processor. However, this is only feasible if the run-time reconfiguration of new tasks is fast enough, so as not to delay application execution. Currently, this is opposed by architectural constraints intrinsic to current Field-Programmable Logic Array (FPGA) architectures. Despite all new features exhibited by current FPGAs, architecturally they are still largely based on general-purpose architectures that are inadequate for the demands of reconfigurable computing. Large configuration file sizes and poor hardware and software support for partial and dynamic reconfiguration limits the acceleration that reconfigurable computing may bring to applications. The objective of this work is the identification of the architectural limitations exhibited by current FPGAs that prevent reconfigurable computing systems to achieve a high efficiency and performance and the proposal of alternatives to its resolution.
- A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-based FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsThis poster presents the first truly non-intrusive structural concurrent test approach, aimed to test partial and dynamically reconfigurable SRAM-based FPGAs without disturbing its operation. This is accomplished by using a new methodology to carry out the replication of active Configurable Logic Blocks (CLBs), i.e. CLBs that are part of an implemented function that is actually being used by the system, releasing it to be tested in a way that is completely transparent to the system.
- Dynamically Rotate And Free for Test: The Path for FPGA Concurrent TestPublication . Gericota, Manuel G.; Alves, Gustavo R.; Ferreira, J. M. MartinsDynamically reconfigurable systems have benefited from a new class of FPGAs, recently introduced into the market, that enables partial and dynamic reconfiguration. While enabling concurrent reconfiguration without disturbing system operation, this technology also raises a new test challenge: to assure a continuously fault free operation independently of the circuit present after the reconfiguration process. A new structural concurrent test method, recently proposed by the authors and based in the principle of replicating and freeing the resources to be tested, raised several questions, one of them being: What strategy to follow in the process of dynamically replicate and free those resources? This paper presents a strategy on how to free the resources to be tested and the results of a series of simulation experiments made with the objective of finding the best methodology to achieve it.
- Run-time Management of the Logic Resources on Reconfigurable SystemsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsDynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have their functionality partially modified at run-time without stopping the operation of the whole system. The efficient management of the logic space available is one of the biggest problems faced by these systems. When the sequence of reconfigurations to be performed is not predictable, resource allocation decisions have to be made on-line. A rearrangement may be necessary to get enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance. A new software tool that helps to handle the problems posed by the consecutive reconfiguration of the same logic space is presented in this paper. This tool uses a novel on- -line rearrangement procedure to solve fragmentation problems and to rearrange the logic space in a way completely transparent to the applications currently running.