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The RAT technique for concurrent test of dynamically reconfigurable hardware
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Orientador(es)
Resumo(s)
A new class of FPGAs that enable partial and
dynamic reconfiguration has been recently
introduced into the market, opening exciting
possibilities for dynamically reconfigurable
hardware systems. While enabling concurrent
reconfiguration without disturbing system operation,
this technology also raises a new test challenge: the
reconfiguration process can activate faults which
would otherwise not be visible. This paper proposes
a structural concurrent test method that reuses the
IEEE 1149.1 infrastructure, exploiting the same
dynamic and partially reconfigurable features
underlying this test challenge.
Descrição
Palavras-chave
FPGAs Reconfigurable systems