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- Run-time defragmentation for dynamically reconfigurable hardwarePublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, José M.Reconfigurable computing experienced a considerable expansion in the last few years, due in part to the fast run-time partial reconfiguration features offered by recent SRAM-based Field Programmable Gate Arrays (FPGAs), which allowed the implementation in real-time of dynamic resource allocation strategies, with multiple independent functions from different applications sharing the same logic resources in the space and temporal domains. However, when the sequence of reconfigurations to be performed is not predictable, the efficient management of the logic space available becomes the greatest challenge posed to these systems. Resource allocation decisions have to be made concurrently with system operation, taking into account function priorities and optimizing the space currently available. As a consequence of the unpredictability of this allocation procedure, the logic space becomes fragmented, with many small areas of free resources failing to satisfy most requests and so remaining unused. A rearrangement of the currently running functions is therefore necessary, so as to obtain enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance. A novel active relocation procedure for Configurable Logic Blocks (CLBs) is herein presented, able to carry out online rearrangements, defragmenting the available FPGA resources without disturbing functions currently running.
- On-line defragmentation for run-time partially reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, José M.Dynamically reconfigurable systems have benefited from a new class of FPGAs recently introduced into the market, which allow partial and dynamic reconfiguration at run-time, enabling multiple independent functions from different applications to share the same device, swapping resources as needed. When the sequence of tasks to be performed is not predictable, resource allocation decisions have to be made on-line, fragmenting the FPGA logic space. A rearrangement may be necessary to get enough contiguous space to efficiently implement incoming functions, to avoid spreading their components and, as a result, degrading their performance. This paper presents a novel active replication mechanism for configurable logic blocks (CLBs), able to implement on-line rearrangements, defragmenting the available FPGA resources without disturbing those functions that are currently running.
- Reliability and availability in reconfigurable computing: a basis for a common solutionPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, José M.Dynamically reconfigurable SRAM-based field-programmable gate arrays (FPGAs) enable the implementation of reconfigurable computing systems where several applications may be run simultaneously, sharing the available resources according to their own immediate functional requirements. To exclude malfunctioning due to faulty elements, the reliability of all FPGA resources must be guaranteed. Since resource allocation takes place asynchronously, an online structural test scheme is the only way of ensuring reliable system operation. On the other hand, this test scheme should not disturb the operation of the circuit, otherwise availability would be compromised. System performance is also influenced by the efficiency of the management strategies that must be able to dynamically allocate enough resources when requested by each application. As those resources are allocated and later released, many small free resource blocks are created, which are left unused due to performance and routing restrictions. To avoid wasting logic resources, the FPGA logic space must be defragmented regularly. This paper presents a non-intrusive active replication procedure that supports the proposed test methodology and the implementation of defragmentation strategies, assuring both the availability of resources and their perfect working condition, without disturbing system operation.
- Programmable Logic Devices: a test approach for the input / output pad-to-pin interconnectionsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsIn the last few years, an increasing use of Programmable Logic Devices (PLDs) in the development of new embedded and systems-on-a-chip (SoC) solutions created the need of new test procedures for this kind of components. Several approaches, depending on the type of PLDs used, were proposed in the literature, addressing the test of the configurable logic array, the interconnection arrays and the configuration memory. However, very little work has been done concerning the specific test of Input/Output Blocks (IOBs) and pad-to-pin bonds. In this paper, a method aimed at covering the test of the IOBs structure in reprogrammable PLDs is proposed. The interconnections between IOBs and other components or connectors at board level are also targeted, benefiting from the availability of Boundary Scan Test (BST) cells on the IOBs of the major PLD families and from the use of “active connectors”.
- DRAFT: An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsReconfigurable systems have benefited of the novel partial dynamic reconfiguration features of recent FPGA devices. Enabling the concurrent reconfiguration without disturbing system operation, this technology has raised a new test challenge: to assure a continuously fault free operation, independently of the circuit present after many reconfiguration processes, testing the FPGA without disturbing the whole system operation. Re-using the IEEE 1149.1 infrastructure, already widely used for In-System Programming, and exploiting the same dynamic and partially reconfigurable features underlying this test challenge, this paper develops a new structural concurrent test approach able to detect faults and introduce fault tolerance features, without disturbing system operation, in the field and throughout its lifetime.
- An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsThe use of partial and dynamically reconfigurable FPGAs in reconfigurable systems opens exciting possibilities, since they enable the concurrent reconfiguration of part of the system without interrupting its operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of failures after many reconfiguration processes. New methods of test and fault tolerance are therefore required, capable of ensuring system reliability. This paper presents improvements to our RaT Freed Resources technique, originally present in [1], a structural concurrent test approach able to detect and diagnosis faults without disturbing system operation, throughout its lifetime.
- DRAFT: A Scanning Test Methodology for Dynamic and Partially Reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsA new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the IEEE 1149.1 Boundary Scan test infrastructure, already widely employed for In-System Programming.
- Testando ...Publication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsOs dispositivos lógicos reconfiguráveis, nomeadamente as FPGAs (Field Programmable Gate Arrays), conheceram uma considerável expansão nos últimos anos. A utilização deste tipo de componentes permite uma poupança de espaço nas placas de circuito impresso e uma mais rápida transição do projecto para o mercado, com um nível inigualável de flexibilidade quando comparado com a tradicional lógica discreta com funcionalidade pré-definida. Estas vantagens foram reforçadas pelo recente aparecimento de FPGAs dinâmica e parcialmente reconfiguráveis (de que a família Virtex da Xilinx é um exemplo), as quais permitem a adaptação dinâmica das funções implementadas pelo hardware a uma aplicação ou a um sistema em particular, sem interromper o funcionamento de todo o sistema, isto é, a funcionalidade destes dispositivos pode ser modificada sem que tal implique a sua paragem ou a do sistema em que se encontram inseridos. Esta nova possibilidade levanta, no entanto, uma questão: como garantir que, independentemente da funcionalidade implementada após múltiplos processos de reconfiguração, o sistema continua a operar sem falhas? Este trabalho procura dar resposta a esta questão propondo um novo método de teste estrutural concorrente, baseado no princípio da replicação e libertação de recursos para serem testados.
- On-line Testing of FPGA Logic Blocks Using Active ReplicationPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, José M.This paper presents a novel on-line test method for partial and dynamically reconfigurable FPGAs, based on the active replication of configurable logic blocks (CLBs). Each CLB in the FPGA is released for test and again made available to be reused if fault-free, or removed from operation if faulty. The proposed method continuously scans the whole FPGA without disturbing system operation. It implies a very low overhead at chip level, since all the test actions are carried out through the IEEE 1149.1 standard boundary-scan architecture and test access port. Moreover, it presents the additional benefit of correcting transient faults, such as single event upsets in space environments, which would otherwise become permanent faults and most likely introduce functional restrictions or even halt the system.
- A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-based FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsThis poster presents the first truly non-intrusive structural concurrent test approach, aimed to test partial and dynamically reconfigurable SRAM-based FPGAs without disturbing its operation. This is accomplished by using a new methodology to carry out the replication of active Configurable Logic Blocks (CLBs), i.e. CLBs that are part of an implemented function that is actually being used by the system, releasing it to be tested in a way that is completely transparent to the system.