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DRAFT: An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs
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Orientador(es)
Resumo(s)
Reconfigurable systems have benefited of the novel
partial dynamic reconfiguration features of recent FPGA
devices. Enabling the concurrent reconfiguration without
disturbing system operation, this technology has raised a
new test challenge: to assure a continuously fault free
operation, independently of the circuit present after many
reconfiguration processes, testing the FPGA without
disturbing the whole system operation.
Re-using the IEEE 1149.1 infrastructure, already
widely used for In-System Programming, and exploiting
the same dynamic and partially reconfigurable features
underlying this test challenge, this paper develops a new
structural concurrent test approach able to detect faults
and introduce fault tolerance features, without disturbing
system operation, in the field and throughout its lifetime.
Descrição
Palavras-chave
FPGA IEEE 1149.1