Browsing by Author "Silva, Miguel L."
Now showing 1 - 10 of 15
Results Per Page
Sort Options
- Active Replication: Towards a Truly SRAM-based FPGA On-Line Concurrent TestingPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsThe reusing of the same hardware resources to implement speed-critical algorithms, without interrupting system operation, is one of the main reasons for the increasing use of reconfigurable computing platforms, employing complex SRAM-based FPGAs. However, new semiconductor manufacturing technologies increase the probability of lifetime operation failures, requiring new on-line testing / fault-tolerance methods able to improve the dependability of the systems where they are included. The Active Replication technique presented in this paper consists of a set of procedures that enables the implementation of a truly non-intrusive structural on-line concurrent testing approach, detecting and avoiding permanent faults and correcting errors due to transient faults. In relation to a previous technique proposed by the authors as part of the DRAFT FPGA concurrent test methodology, the Active Replication technique extends the range of circuits that can be replicated, by introducing a novel method with very low silicon overhead.
- An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsThe use of partial and dynamically reconfigurable FPGAs in reconfigurable systems opens exciting possibilities, since they enable the concurrent reconfiguration of part of the system without interrupting its operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of failures after many reconfiguration processes. New methods of test and fault tolerance are therefore required, capable of ensuring system reliability. This paper presents improvements to our RaT Freed Resources technique, originally present in [1], a structural concurrent test approach able to detect and diagnosis faults without disturbing system operation, throughout its lifetime.
- AR2T: Implementing a Truly SRAM-based FPGA On-Line Concurrent TestingPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsThe new partial and dynamic reconfigurable features offered by new generations of SRAM-based FPGAs may be used to improve the dependability of reconfigurable hardware platforms through the implementation of on-line concurrent testing / fault-tolerance mechanisms. However, such mechanisms call for the development of new test strategies that do not interfere with the current system functionality. The AR2T (Active Replication and Release for Testing) technique is a set of procedures that enables the implementation of a truly non-intrusive structural on-line concurrent testing approach, detecting and avoiding permanent faults and correcting errors due to transient faults. The experimental results presented prove the effectiveness of these solutions. In relation to a previous technique proposed by the authors as part of the DRAFT FPGA concurrent test methodology, AR2T extends the range of circuits that can be replicated, by introducing a small replication aid block.
- Concurrent replication of active logic blocks: A core solution for online testing and logic space defragmentation in reconfigurable systemsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Martins, J.M.Partial and dynamically reconfigurable SRAM-based FPGAs (Field Programmable Gate Arrays) enable the implementation of reconfigurable systems hosting several applications simultaneously, which share the available resources according to the functional requirements that are present at any given moment. Time and space sharing strategies enabled the concept of virtual hardware, supporting the concurrent implementation of applications which would otherwise require far more complex resources. However, the performance of these applications (e.g. execution speed and reliability, activation delay) is directly influenced by the efficiency of the management strategies that allocate the logic space to the various functions that are waiting to be activated (each function requiring a specific amount of logic resources). Because the activation requests are in most cases not predictable, all resource allocation decisions have to be made online. The consequences of such working contexts are twofold: All FPGA resources must be tested regularly, to exclude malfunctioning due to the allocation of faulty elements. Since the process of launching / halting active functions takes place asynchronously at any given moment, an online concurrent test scheme is the only way of ensuring reliable system operation and predictable fault detection latency; As the resources are allocated to functions and later released, many small “islands” of free resources are created. If these areas become too small, they will be left unused due to routing restrictions. The defragmentation of the FPGA logic space must therefore be carried out regularly, to avoid the wasting of logic resources. This paper presents a non-intrusive solution for the concurrent replication of active logic blocks (i.e. logic blocks that are being used to implement part of an active function), transferring their functionality to fault-free resources that are available in the FPGA logic space. This replication scheme is then used as the core of an online concurrent test strategy that scans the complete FPGA, reusing the available 1149.1 test infrastructure to carry out a structural test of each logic block that has just been released. The overhead of the proposed solution, in terms of the number of configurable logic resources required for its implementation, as well as its performance (e.g. the resulting fault detection latency), are quantified. Further to the test aspects, an online concurrent defragmentation strategy based on the same replication scheme is also proposed. A rearrangement of the available logic space is carried out by selectively releasing active logic blocks, with the objective of enforcing the adjacency of those blocks that share the implementation of a common function, and the creation of wider pools of logic resources that may be used to implement new functions.
- DRAFT: A Scanning Test Methodology for Dynamic and Partially Reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsA new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the IEEE 1149.1 Boundary Scan test infrastructure, already widely employed for In-System Programming.
- DRAFT: An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsReconfigurable systems have benefited of the novel partial dynamic reconfiguration features of recent FPGA devices. Enabling the concurrent reconfiguration without disturbing system operation, this technology has raised a new test challenge: to assure a continuously fault free operation, independently of the circuit present after many reconfiguration processes, testing the FPGA without disturbing the whole system operation. Re-using the IEEE 1149.1 infrastructure, already widely used for In-System Programming, and exploiting the same dynamic and partially reconfigurable features underlying this test challenge, this paper develops a new structural concurrent test approach able to detect faults and introduce fault tolerance features, without disturbing system operation, in the field and throughout its lifetime.
- Dynamic Replication: The Core of a Truly Non-Intrusive SRAM-Based FPGA Structural Concurrent Test MethodologyPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsThe increasing use of reconfigurable computing platforms, employing SRAM-based FPGAs, opens exciting new possibilities since they enable the reutilization of the same hardware resources to implement speed-critical computational tasks, without interrupting system operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of lifetime operation failures, requiring new test / f ault-tolerance methods capable of assuring the reliability of the system. Structural concurrent test procedures become particularly important in this context, since it is now possible to replicate and release for test internal FPGA resources, concurrently with — but not affecting —system operation. A new dynamic replication process of active Configurable Logic Blocks (CLBs) is presented in this paper, which enables the implementation of a truly non-intrusive structural concurrent test approach. The experimental results presented prove the effectiveness of this solution.
- A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-based FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsThis poster presents the first truly non-intrusive structural concurrent test approach, aimed to test partial and dynamically reconfigurable SRAM-based FPGAs without disturbing its operation. This is accomplished by using a new methodology to carry out the replication of active Configurable Logic Blocks (CLBs), i.e. CLBs that are part of an implemented function that is actually being used by the system, releasing it to be tested in a way that is completely transparent to the system.
- On-line defragmentation for run-time partially reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, José M.Dynamically reconfigurable systems have benefited from a new class of FPGAs recently introduced into the market, which allow partial and dynamic reconfiguration at run-time, enabling multiple independent functions from different applications to share the same device, swapping resources as needed. When the sequence of tasks to be performed is not predictable, resource allocation decisions have to be made on-line, fragmenting the FPGA logic space. A rearrangement may be necessary to get enough contiguous space to efficiently implement incoming functions, to avoid spreading their components and, as a result, degrading their performance. This paper presents a novel active replication mechanism for configurable logic blocks (CLBs), able to implement on-line rearrangements, defragmenting the available FPGA resources without disturbing those functions that are currently running.
- On-line Testing of FPGA Logic Blocks Using Active ReplicationPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, José M.This paper presents a novel on-line test method for partial and dynamically reconfigurable FPGAs, based on the active replication of configurable logic blocks (CLBs). Each CLB in the FPGA is released for test and again made available to be reused if fault-free, or removed from operation if faulty. The proposed method continuously scans the whole FPGA without disturbing system operation. It implies a very low overhead at chip level, since all the test actions are carried out through the IEEE 1149.1 standard boundary-scan architecture and test access port. Moreover, it presents the additional benefit of correcting transient faults, such as single event upsets in space environments, which would otherwise become permanent faults and most likely introduce functional restrictions or even halt the system.