Browsing by Issue Date, starting with "2003-10"
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- Comparison between two common methods for measuring Giardia lamblia susceptibility to antiparasitic drugs in vitroPublication . Cruz, Agostinho; Sousa, M. Isaura; Azeredo, Zaida; Silva, M. Carolina; Sousa, J.C. Figueiredo de; Manso, Olga; Cabral, MiguelIn this study a comparison between two different methods for measuring the susceptibility of Giardia lamblia trophozoites to metronidazole and albendazole is performed. Modifications of Meloni’s method, based on the loss of adherence of parasites to surfaces, and the Hill method, based on the loss of parasite division capacity, are compared. A logistic model was used to calculate the inhibitory concentrations IC10, IC50 and IC90 that were further compared using the respective standard errors. The results obtained, after contact of parasites with the antiparasitic drugs for 24 h, show that the adherence method is more sensitive than the multiplication method for low and moderate inhibitory concentrations of albendazole. Conversely for metronidazole the multiplication method seems to be more sensitive for high inhibitory concentrations of the drug. For screening the IC50, both methods seem to be effective, however, the inhibition of adherence method have even better performance for the benzimidazole like drugs.
- Concurrent replication of active logic blocks: A core solution for online testing and logic space defragmentation in reconfigurable systemsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Martins, J.M.Partial and dynamically reconfigurable SRAM-based FPGAs (Field Programmable Gate Arrays) enable the implementation of reconfigurable systems hosting several applications simultaneously, which share the available resources according to the functional requirements that are present at any given moment. Time and space sharing strategies enabled the concept of virtual hardware, supporting the concurrent implementation of applications which would otherwise require far more complex resources. However, the performance of these applications (e.g. execution speed and reliability, activation delay) is directly influenced by the efficiency of the management strategies that allocate the logic space to the various functions that are waiting to be activated (each function requiring a specific amount of logic resources). Because the activation requests are in most cases not predictable, all resource allocation decisions have to be made online. The consequences of such working contexts are twofold: All FPGA resources must be tested regularly, to exclude malfunctioning due to the allocation of faulty elements. Since the process of launching / halting active functions takes place asynchronously at any given moment, an online concurrent test scheme is the only way of ensuring reliable system operation and predictable fault detection latency; As the resources are allocated to functions and later released, many small “islands” of free resources are created. If these areas become too small, they will be left unused due to routing restrictions. The defragmentation of the FPGA logic space must therefore be carried out regularly, to avoid the wasting of logic resources. This paper presents a non-intrusive solution for the concurrent replication of active logic blocks (i.e. logic blocks that are being used to implement part of an active function), transferring their functionality to fault-free resources that are available in the FPGA logic space. This replication scheme is then used as the core of an online concurrent test strategy that scans the complete FPGA, reusing the available 1149.1 test infrastructure to carry out a structural test of each logic block that has just been released. The overhead of the proposed solution, in terms of the number of configurable logic resources required for its implementation, as well as its performance (e.g. the resulting fault detection latency), are quantified. Further to the test aspects, an online concurrent defragmentation strategy based on the same replication scheme is also proposed. A rearrangement of the available logic space is carried out by selectively releasing active logic blocks, with the objective of enforcing the adjacency of those blocks that share the implementation of a common function, and the creation of wider pools of logic resources that may be used to implement new functions.
- Simulation and dynamical analysis of freeway trafficPublication . Figueiredo, Lino; Tenreiro Machado, J. A.; Ferreira, José RuiThis paper discusses the problem of modelling and simulation of traffic systems, and presents the traffic simulator SITS (Simulator of Intelligent Transportation Systems). The SITS is based on a microscopic simulation approach considering different types of vehicles, drivers and roads. A dynamical analysis of several traffic phenomena is then addressed.
- On the dynamics analysis of freeway trafficPublication . Figueiredo, Lino; Tenreiro Machado, J. A.; Ferreira, José RuiThis paper presents the Simulator of Intelligent Transportation Systems (SITS). The SITS is based on a microscopic simulation approach to reproduce real traffic conditions in an urban or non-urban network and considers different type of vehicles, drivers and roads. A dynamical analysis of several traffic phenomena is then addressed. The results of using classical system theory tools point out that it is possible to study traffic systems, taking advantage on the knowledge gathered with automatic control algorithms. In this line of thought, it was also presented a new modelling formalism based on the embedding of statistics and Fourier transform.