Percorrer por autor "Gericota, Manuel G."
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- Active Replication: Towards a Truly SRAM-based FPGA On-Line Concurrent TestingPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsThe reusing of the same hardware resources to implement speed-critical algorithms, without interrupting system operation, is one of the main reasons for the increasing use of reconfigurable computing platforms, employing complex SRAM-based FPGAs. However, new semiconductor manufacturing technologies increase the probability of lifetime operation failures, requiring new on-line testing / fault-tolerance methods able to improve the dependability of the systems where they are included. The Active Replication technique presented in this paper consists of a set of procedures that enables the implementation of a truly non-intrusive structural on-line concurrent testing approach, detecting and avoiding permanent faults and correcting errors due to transient faults. In relation to a previous technique proposed by the authors as part of the DRAFT FPGA concurrent test methodology, the Active Replication technique extends the range of circuits that can be replicated, by introducing a novel method with very low silicon overhead.
- An HDL Approach to Board-Level BISTPublication . Alves, Gustavo R.; Gericota, Manuel G.; Ramalho, José L.; Ferreira, José M.Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analysed, and a corresponding set of testability building blocks are proposed. A low-cost and maximum-flexibility solution is described, which implements these blocks on medium-complexity PLDs, using a simple and powerful HDL.
- An integrated reusable remote laboratory to complement electronics teachingPublication . Sousa, Nuno; Alves, Gustavo R.; Gericota, Manuel G.The great majority of the courses on science and technology areas where lab work is a fundamental part of the apprenticeship was not until recently available to be taught at distance. This reality is changing with the dissemination of remote laboratories. Supported by resources based on new information and communication technologies, it is now possible to remotely control a wide variety of real laboratories. However, most of them are designed specifically to this purpose, are inflexible and only on its functionality they resemble the real ones. In this paper, an alternative remote lab infrastructure devoted to the study of electronics is presented. Its main characteristics are, from a teacher's perspective, reusability and simplicity of use, and from a students' point of view, an exact replication of the real lab, enabling them to complement or finish at home the work started at class. The remote laboratory is integrated in the Learning Management System in use at the school, and therefore, may be combined with other web experiments and e-learning strategies, while safeguarding security access issues.
- An On-line Concurrent Test for Partial and Dynamically Reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsThe use of partial and dynamically reconfigurable FPGAs in reconfigurable systems opens exciting possibilities, since they enable the concurrent reconfiguration of part of the system without interrupting its operation. Nevertheless, larger dies and the use of smaller submicron scales in the manufacturing of this new kind of FPGAs increase the probability of failures after many reconfiguration processes. New methods of test and fault tolerance are therefore required, capable of ensuring system reliability. This paper presents improvements to our RaT Freed Resources technique, originally present in [1], a structural concurrent test approach able to detect and diagnosis faults without disturbing system operation, throughout its lifetime.
- AR2T: Implementing a Truly SRAM-based FPGA On-Line Concurrent TestingPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsThe new partial and dynamic reconfigurable features offered by new generations of SRAM-based FPGAs may be used to improve the dependability of reconfigurable hardware platforms through the implementation of on-line concurrent testing / fault-tolerance mechanisms. However, such mechanisms call for the development of new test strategies that do not interfere with the current system functionality. The AR2T (Active Replication and Release for Testing) technique is a set of procedures that enables the implementation of a truly non-intrusive structural on-line concurrent testing approach, detecting and avoiding permanent faults and correcting errors due to transient faults. The experimental results presented prove the effectiveness of these solutions. In relation to a previous technique proposed by the authors as part of the DRAFT FPGA concurrent test methodology, AR2T extends the range of circuits that can be replicated, by introducing a small replication aid block.
- Assessing Defragmentation Strategies for FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Lemos, Luís; Ferreira, José M.Fragmentation on dynamically reconfigurable FPGAs is currently a major obstacle to the efficient management of its logic space. When resource allocation decisions have to be made at run-time a relocation of currently running functions may be necessary to release enough contiguous resources to implement incoming functions. Relocation should have into account any specifics of function’s functionality and also those of the FPGA’s architecture as to not affect system’s performance. A simple and fast method to assess performance degradation of a function during relocation is proposed in this paper. This method is based on previous function labelling and on the new concept of proximity vectors.
- A comparative analysis of fault injection methods via enhanced on-chip debug infrastructuresPublication . Fidalgo, André Vaz; Alves, Gustavo R.; Gericota, Manuel G.; Ferreira, José M.On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.
- Concurrent replication of active logic blocks: A core solution for online testing and logic space defragmentation in reconfigurable systemsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Martins, J.M.Partial and dynamically reconfigurable SRAM-based FPGAs (Field Programmable Gate Arrays) enable the implementation of reconfigurable systems hosting several applications simultaneously, which share the available resources according to the functional requirements that are present at any given moment. Time and space sharing strategies enabled the concept of virtual hardware, supporting the concurrent implementation of applications which would otherwise require far more complex resources. However, the performance of these applications (e.g. execution speed and reliability, activation delay) is directly influenced by the efficiency of the management strategies that allocate the logic space to the various functions that are waiting to be activated (each function requiring a specific amount of logic resources). Because the activation requests are in most cases not predictable, all resource allocation decisions have to be made online. The consequences of such working contexts are twofold: All FPGA resources must be tested regularly, to exclude malfunctioning due to the allocation of faulty elements. Since the process of launching / halting active functions takes place asynchronously at any given moment, an online concurrent test scheme is the only way of ensuring reliable system operation and predictable fault detection latency; As the resources are allocated to functions and later released, many small “islands” of free resources are created. If these areas become too small, they will be left unused due to routing restrictions. The defragmentation of the FPGA logic space must therefore be carried out regularly, to avoid the wasting of logic resources. This paper presents a non-intrusive solution for the concurrent replication of active logic blocks (i.e. logic blocks that are being used to implement part of an active function), transferring their functionality to fault-free resources that are available in the FPGA logic space. This replication scheme is then used as the core of an online concurrent test strategy that scans the complete FPGA, reusing the available 1149.1 test infrastructure to carry out a structural test of each logic block that has just been released. The overhead of the proposed solution, in terms of the number of configurable logic resources required for its implementation, as well as its performance (e.g. the resulting fault detection latency), are quantified. Further to the test aspects, an online concurrent defragmentation strategy based on the same replication scheme is also proposed. A rearrangement of the available logic space is carried out by selectively releasing active logic blocks, with the objective of enforcing the adjacency of those blocks that share the implementation of a common function, and the creation of wider pools of logic resources that may be used to implement new functions.
- DRAFT: A Scanning Test Methodology for Dynamic and Partially Reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsA new class of FPGAs that enable partial and dynamic reconfiguration without disturbing system operation, raised a new test challenge: how to assure a continuously fault free operation, independently of the circuit present after many reconfiguration processes. A new on-line test method for those FPGAs is proposed, based on a scanning methodology and in the reuse of the IEEE 1149.1 Boundary Scan test infrastructure, already widely employed for In-System Programming.
- DRAFT: An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, J. M. MartinsReconfigurable systems have benefited of the novel partial dynamic reconfiguration features of recent FPGA devices. Enabling the concurrent reconfiguration without disturbing system operation, this technology has raised a new test challenge: to assure a continuously fault free operation, independently of the circuit present after many reconfiguration processes, testing the FPGA without disturbing the whole system operation. Re-using the IEEE 1149.1 infrastructure, already widely used for In-System Programming, and exploiting the same dynamic and partially reconfigurable features underlying this test challenge, this paper develops a new structural concurrent test approach able to detect faults and introduce fault tolerance features, without disturbing system operation, in the field and throughout its lifetime.