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Advisor(s)
Abstract(s)
Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analysed, and a corresponding set of testability building blocks are proposed. A low-cost and maximum-flexibility solution is described, which implements these blocks on medium-complexity PLDs, using a simple and powerful HDL.
Description
Keywords
Design for testability Boundary scan
Citation
Publisher
Institute of Electrical and Electronics Engineers