ISEP - CIETI - Centro de Inovação em Engenharia e Tecnologia Industrial
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O grupo CIETI (Centro de Inovação em Engenharia e Tecnologia Industrial) tem como objectivo promover a investigação para a criação e desenvolvimento de novos produtos, processos e sistemas que contribuam para a inovação na indústria.
O grupo também dá suporte à educação científica no Instituto Superior de Engenharia do Porto integrando alunos de mestrado e co-orientando teses de doutoramento.
O grupo CIETI é um grupo de investigação e desenvolvimento multidisciplinar do Instituto Superior de Engenharia do Porto. As actividades do grupo dividem-se em quatro linhas de trabalho:
Biomateriais e nanotecnologias
Energia e ambiente
Engenharia e processo
Laboratórios remotos e sistemas de teste e depuração
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- An HDL Approach to Board-Level BISTPublication . Alves, Gustavo R.; Gericota, Manuel G.; Ramalho, José L.; Ferreira, José M.Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analysed, and a corresponding set of testability building blocks are proposed. A low-cost and maximum-flexibility solution is described, which implements these blocks on medium-complexity PLDs, using a simple and powerful HDL.
- IEEE 1149.1 compliance-enable pin(s): a solution for embedded microprocessor-based systems debug and testPublication . Alves, Gustavo R.; Ferreira, José M.Microprocessor-based systems are usually debugged with the help of in-circuit emulators and logic analysers. However, these traditional debug tools cannot be used when the microprocessor is an embedded core. To overcome this problem we propose the use of an embedded debug and test infrastructure and the IEEE 1149.1 compliance-enable mode to implement the basic functionality provided by an In-circuit emulator and a logic analyser.
- From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1Publication . Alves, Gustavo R.; Ferreira, José M.The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.
- Board-level prototype validation: a built-in controller and extended BST architecturePublication . Alves, Gustavo R.; Amaral, T.; Ferreira, José M.Prototype validation is a major concern in modern electronic product design and development. Simulation, structural test, functional and timing debug are all forming parts of the validation process, although very often addressed as dissociated tasks. In this paper we describe an integrated approach to board-level prototype validation, based on a set of mandatory/optional BST instructions and a built-in controller for debug and test, that addresses the late mentioned tasks as inherent parts of a whole process
- A system verification strategy based on the BST infrastructurePublication . Alves, Gustavo R.; Ferreira, José M.A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.
- Projeto para o Teste e Depuração com Base nas Arquiteturas IEEE 1149.1 e 1149.4Publication . Alves, Gustavo R.; Ferreira, José M.A infraestrutura Boundary Scan Test (BST), definida na norma IEEE 1149.1, tem sido tradicionalmente utilizada para o teste estrutural de Cartas de Circuito Impresso (CCI) na fase de produção. O seu aparecimento deveu-se, entre outras razões, à crescente dificuldade das tradicionais tecnologias de teste de CCI (o teste in-circuit e o teste funcional) em lidar com os novos tipos de encapsulamento de Circuitos Integrados (CI) e com a sua crescente complexidade. A utilização de CI de montagem superficial veio reduzir o distanciamento entre os pinos e permitir a montagem de componentes em ambos os lados da CCI, dificultando assim o acesso físico requerido pelo teste in- circuit. A crescente complexidade veio por sua vez dificultar a propagação de valores no interior da CCI, diminuindo assim a qualidade do teste funcional.
- Implementing a Self- Checking PROFIBUS SlavePublication . Krug, Margrit R.; Lubaszewski, Marcelo S.; Ferreira, Jose M.; Alves, Gustavo R.This work presents the study and preliminary results of the high level implementation of a self-checking Profibus slave. From an existing VHDL description of the device, a test strategy was studied and implemented, so that the whole circuit has embedded test structures capable to perform at-speed test of the slave. In this paper, we show the used test strategies and implementation results achieved from a synthesis process in a FPGA environment.
- From Circuit Simulation to Circuit Verification: An Internal + Boundary Scan-based SolutionPublication . Alves, Gustavo R.; Krug, Margrit R.; Lubaszewski, Marcelo; Ferreira, Jose M.Matching the results obtained from circuit simulation with those extracted from circuit functioning is a common stage of the final verification process. Many current verification techniques use the I/O vectors produced during functional and / or timing simulation, for creating the test vectors to be applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes such a solution for verifying digital designs implemented in currently commercial available CPLDs. The test program is automatically generated from information that encompasses the design & development phase, namely: the file containing the results from simulation, the BSDL file, an internal scan chain description file, and one file containing the user options.
- An Automated Verification Process Based on Scan TechniquePublication . Alves, Gustavo R.; Krug, Margrit R.; Lubaszewski, Marcelo S.; Ferreira, Jose M.Matching the results achieved during circuit simulation with those extracted from circuit functioning is a common verification process. A large number of current verification techniques use the input / output vectors produced during functional simulation as the test vectors applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes a solution for verifying digital designs implemented in currently commercial available CPLDs. All internal flip-flops are included in a scan-chain accessible through the BST infrastructure (using a user-defined optional instruction), while the BS cells are used to apply the input test vectors and capture the circuit responses. These BS cells can either belong to the device-under-test or to other devices, the first controlled through the optional INTEST instruction and the second controlled through the mandatory EXTEST instruction. To speed up the verification process, the test program is automatically generated from information that encompasses the design & development phase.
- Collaborative learning in a qeb-accessible workbenchPublication . Ferreira, José M.; Alves, Gustavo R.; Costa, Ricardo J.; Hine, NickWeb-based course management and delivery is regarded by many institutions as a key factor in an increasingly competitive education and training world, but the systems currently available are largely unsatisfactory in terms of supporting collaborative work and access to practical science facilities. These limitations are less important in areas where “pen-and-paper” courseware is the mainstream, but become unacceptably restrictive when student assignments require real-time teamwork and access to laboratory equipment. This paper presents a web-accessible workbench for electronics design and test, which was developed in the scope of an European IST project entitled PEARL, with the aim of supporting two main features: full web access and collaborative learning facilities.