A system verification strategy based on the BST infrastructure

Alves, Gustavo R.; Ferreira, José M.

http://hdl.handle.net/10400.22/4320

Use this identifier to reference this record.

Name:	Description:	Size:	Format:
69670.pdf		336.46 KB	Adobe PDF	Download

Send Feedback

Authors

Alves, Gustavo R.

Ferreira, José M.

Abstract(s)

A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.