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A system verification strategy based on the BST infrastructure

dc.contributor.authorAlves, Gustavo R.
dc.contributor.authorFerreira, José M.
dc.date.accessioned2014-04-24T11:05:09Z
dc.date.available2014-04-24T11:05:09Z
dc.date.issued1999
dc.description.abstractA good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.por
dc.identifier.doi10.1109/ISCAS.1999.777799
dc.identifier.doi10.1109/ISCAS.1999.777799
dc.identifier.isbn0-7803-5471-0
dc.identifier.urihttp://hdl.handle.net/10400.22/4320
dc.language.isoengpor
dc.peerreviewedyespor
dc.publisherIEEEpor
dc.relation.ispartofseriesCircuits and Systems; Vol. 1
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=777799por
dc.titleA system verification strategy based on the BST infrastructurepor
dc.typeconference object
dspace.entity.typePublication
oaire.citation.conferencePlaceOrlando, FLpor
oaire.citation.endPage38por
oaire.citation.startPage35por
oaire.citation.titleISCAS '99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systemspor
oaire.citation.volumeVol. 1por
person.familyNameAlves
person.givenNameGustavo
person.identifier150015
person.identifier.ciencia-id4210-4DF2-5206
person.identifier.orcid0000-0002-1244-8502
person.identifier.ridI-7876-2014
person.identifier.scopus-author-id7006053908
rcaap.rightsopenAccesspor
rcaap.typeconferenceObjectpor
relation.isAuthorOfPublication01800568-7eaf-41d9-b78d-cf64f7c7381d
relation.isAuthorOfPublication.latestForDiscovery01800568-7eaf-41d9-b78d-cf64f7c7381d

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