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- Run-time defragmentation for dynamically reconfigurable hardwarePublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, José M.Reconfigurable computing experienced a considerable expansion in the last few years, due in part to the fast run-time partial reconfiguration features offered by recent SRAM-based Field Programmable Gate Arrays (FPGAs), which allowed the implementation in real-time of dynamic resource allocation strategies, with multiple independent functions from different applications sharing the same logic resources in the space and temporal domains. However, when the sequence of reconfigurations to be performed is not predictable, the efficient management of the logic space available becomes the greatest challenge posed to these systems. Resource allocation decisions have to be made concurrently with system operation, taking into account function priorities and optimizing the space currently available. As a consequence of the unpredictability of this allocation procedure, the logic space becomes fragmented, with many small areas of free resources failing to satisfy most requests and so remaining unused. A rearrangement of the currently running functions is therefore necessary, so as to obtain enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance. A novel active relocation procedure for Configurable Logic Blocks (CLBs) is herein presented, able to carry out online rearrangements, defragmenting the available FPGA resources without disturbing functions currently running.
- Interactive Exercises on Analysis Methods for DC Linear Electrical CircuitsPublication . Sousa, Pedro A.; Gericota, Manuel G.; Alves, Gustavo R.Electrical Engineering students must learn the fundamentals of electricity in a very short time, due to the increasing number and size of areas addressed on EE courses. While some students have been exposed to those fundamentals during secondary level education, others have not. These circumstances increase the complexity of devising a good approach to motivate all students for learning. One example occurs when teaching the analysis methods for DC Linear Electrical Circuits, where the number of all possible arbitrary choices grows exponentially with the number of circuit branches. While first-time-exposed students are required to learn first how to apply the different analysis methods, the remaining students are required to calculate the total number of possible set of equations that solve the circuit. To serve both student groups, we developed an application that helps understanding the way arbitrary choices affect the set of equations generated for solving a customizable circuit.
- A new approach to assess defragmentation strategies in dynamically reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Lemos, L. F.; Ferreira, José M.Fragmentation on dynamically reconfigurable FPGAs is a major obstacle to the efficient management of the logic space in reconfigurable systems. When resource allocation decisions have to be made at run-time a rearrangement may be necessary to release enough contiguous resources to implement incoming functions. The feasibility of run-time relocation depends on the processing time required to set up rearrangements. Moreover, the performance of the relocated functions should not be affected by this process or otherwise the whole system performance, and even its operation, may be at risk. Relocation should take into account not only specific functional issues, but also the FPGA architecture, since these two aspects are normally intertwined. A simple and fast method to assess performance degradation of a function during relocation and to speed up the defragmentation process, based on previous function labelling and on the application of the Euclidian distance concept, is proposed in this paper.
- Real Time Fault Injection Using On Chip Debug Infrastructures – A Case StudyPublication . Fidalgo, André Vaz; Gericota, Manuel G.; Alves, Gustavo R.; Ferreira, JoséAs electronic devices get smaller and more complex, dependability assurance is becoming fundamental for many mission critical computer based systems. This paper presents a case study on the possibility of using the on-chip debug infrastructures present in most current microprocessors to execute real time fault injection campaigns. The proposed methodology is based on a debugger customized for fault injection and consists of injecting bit-flip type faults on memory elements without modifying or halting the target application. Three different configurations are compared in terms of performance, area overhead and communication bus width. The basic debugger design is easily portable and applicable to different architectures, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.
- Assessing Defragmentation Strategies for FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Lemos, Luís; Ferreira, José M.Fragmentation on dynamically reconfigurable FPGAs is currently a major obstacle to the efficient management of its logic space. When resource allocation decisions have to be made at run-time a relocation of currently running functions may be necessary to release enough contiguous resources to implement incoming functions. Relocation should have into account any specifics of function’s functionality and also those of the FPGA’s architecture as to not affect system’s performance. A simple and fast method to assess performance degradation of a function during relocation is proposed in this paper. This method is based on previous function labelling and on the new concept of proximity vectors.
- On-line defragmentation for run-time partially reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, José M.Dynamically reconfigurable systems have benefited from a new class of FPGAs recently introduced into the market, which allow partial and dynamic reconfiguration at run-time, enabling multiple independent functions from different applications to share the same device, swapping resources as needed. When the sequence of tasks to be performed is not predictable, resource allocation decisions have to be made on-line, fragmenting the FPGA logic space. A rearrangement may be necessary to get enough contiguous space to efficiently implement incoming functions, to avoid spreading their components and, as a result, degrading their performance. This paper presents a novel active replication mechanism for configurable logic blocks (CLBs), able to implement on-line rearrangements, defragmenting the available FPGA resources without disturbing those functions that are currently running.
- Um Laboratório Remoto, Múltiplas PotencialidadesPublication . Sousa, Nuno; Gericota, Manuel G.; Alves, Gustavo R.O ensino à distância padeceu, durante longos anos, de várias limitações ao nível da interacção entre alunos, professores e material didáctico. Essas limitações foram sendo ultrapassadas com recurso aos novos meios de comunicação, de que a internet é, neste caso concreto, exemplo máximo. No entanto, uma das limitações que se tem mostrado mais difícil de superar é a do acesso remoto dos alunos a laboratórios reais. As várias propostas apresentadas até ao momento implicam normalmente um conjunto de recursos próprios e pouco flexíveis para cada trabalho, com um elevado tempo de aprendizagem para a sua implementação. O laboratório remoto apresentado neste artigo tem por base uma plataforma flexível que permite a realização de múltiplos trabalhos sem necessidade de alterações da sua estrutura de base. A sua utilização é bastante simples, não implicando longos ciclos de configuração. A interface com o utilizador é genérica, não necessitando de ser configurada, qualquer que seja a montagem efectuada.
- On-line self-healing of circuits implemented on reconfigurable FPGAsPublication . Gericota, Manuel G.; Lemos, L. F.; Alves, Gustavo R.; Ferreira, José M.To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radiation-induced faults, which affect values stored in memory cells, and to manufacturing imperfections. Fault tolerant implementations, based on Triple Modular Redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like module placement, the effects of multi- bit upsets (MBU) or fault accumulation, have also to be addressed. In case of a fault occurrence the correct operation of the affected module must be restored and/or the current state of the circuit coherently re-established. A solution that enables the autonomous restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in real-time, while keeping the normal operation of the circuit, is presented in this paper.
- A Remote Verification Framework to Assess the Robustness of Circuits to Soft FaultsPublication . Alves, Gustavo R.; Gericota, Manuel G.; Fidalgo, André VazThe growing number of circuits implemented in Field Programmable Gate Arrays (FPGAs) and the increased susceptibility, due to higher integration levels, of these devices to soft faults caused by radiation at ground level is leading the scientific and technical community to the study of new fault tolerant designs and solutions, and how they can be verified and validated. Using fault injection techniques and enhanced debug tools to inject faults in a circuit and observing its behaviour in the presence of such faults, respectively, is a proven solution for the previous verification and validation problem. This paper presents the underlying concepts for a remote verification framework to assess the robustness of circuits to soft faults. It comprises a verification platform and a set of verification services that can be used in a remote or local fashions.
- A framework for fault tolerant real time systems based on reconfigurable FPGAsPublication . Gericota, Manuel G.; Lemos, L. F.; Alves, Gustavo R.; Barbosa, M. M.; Ferreira, José M.To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.