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Orientador(es)
Resumo(s)
As electronic devices get smaller and more complex,
dependability assurance is becoming fundamental for many
mission critical computer based systems. This paper presents a
case study on the possibility of using the on-chip debug
infrastructures present in most current microprocessors to
execute real time fault injection campaigns. The proposed
methodology is based on a debugger customized for fault
injection and consists of injecting bit-flip type faults on memory
elements without modifying or halting the target application.
Three different configurations are compared in terms of
performance, area overhead and communication bus width. The
basic debugger design is easily portable and applicable to
different architectures, providing a flexible and efficient
mechanism for verifying and validating fault tolerant
components.
Descrição
Palavras-chave
Computer Fault Tolerance Fault Injection On Chip Debug Reliability