ISEP – CIETI – Comunicações em eventos científicos
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- From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1Publication . Alves, Gustavo R.; Ferreira, José M.The increasing complexity of VLSI circuits and the reduced accessibility of modern packaging and mounting technologies restrict the usefulness of conventional in-circuit debugging tools, such as in-circuit emulators for microprocessors and microcontrollers. However, this same trend enables the development of more complex products, which in turn require more powerful debugging tools. These conflicting demands could be met if the standard scan test infrastructures now common in most complex components were able to match the debugging requirements of design verification and prototype validation. This paper analyses the main debug requirements in the design of microprocessor-based applications and the feasibility of their implementation using the mandatory, optional and additional operating modes of the standard IEEE 1149.1 test infrastructure.
- Board-level prototype validation: a built-in controller and extended BST architecturePublication . Alves, Gustavo R.; Amaral, T.; Ferreira, José M.Prototype validation is a major concern in modern electronic product design and development. Simulation, structural test, functional and timing debug are all forming parts of the validation process, although very often addressed as dissociated tasks. In this paper we describe an integrated approach to board-level prototype validation, based on a set of mandatory/optional BST instructions and a built-in controller for debug and test, that addresses the late mentioned tasks as inherent parts of a whole process
- A system verification strategy based on the BST infrastructurePublication . Alves, Gustavo R.; Ferreira, José M.A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.
- Projeto para o Teste e Depuração com Base nas Arquiteturas IEEE 1149.1 e 1149.4Publication . Alves, Gustavo R.; Ferreira, José M.A infraestrutura Boundary Scan Test (BST), definida na norma IEEE 1149.1, tem sido tradicionalmente utilizada para o teste estrutural de Cartas de Circuito Impresso (CCI) na fase de produção. O seu aparecimento deveu-se, entre outras razões, à crescente dificuldade das tradicionais tecnologias de teste de CCI (o teste in-circuit e o teste funcional) em lidar com os novos tipos de encapsulamento de Circuitos Integrados (CI) e com a sua crescente complexidade. A utilização de CI de montagem superficial veio reduzir o distanciamento entre os pinos e permitir a montagem de componentes em ambos os lados da CCI, dificultando assim o acesso físico requerido pelo teste in- circuit. A crescente complexidade veio por sua vez dificultar a propagação de valores no interior da CCI, diminuindo assim a qualidade do teste funcional.
- Implementing a Self- Checking PROFIBUS SlavePublication . Krug, Margrit R.; Lubaszewski, Marcelo S.; Ferreira, Jose M.; Alves, Gustavo R.This work presents the study and preliminary results of the high level implementation of a self-checking Profibus slave. From an existing VHDL description of the device, a test strategy was studied and implemented, so that the whole circuit has embedded test structures capable to perform at-speed test of the slave. In this paper, we show the used test strategies and implementation results achieved from a synthesis process in a FPGA environment.
- From Circuit Simulation to Circuit Verification: An Internal + Boundary Scan-based SolutionPublication . Alves, Gustavo R.; Krug, Margrit R.; Lubaszewski, Marcelo; Ferreira, Jose M.Matching the results obtained from circuit simulation with those extracted from circuit functioning is a common stage of the final verification process. Many current verification techniques use the I/O vectors produced during functional and / or timing simulation, for creating the test vectors to be applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes such a solution for verifying digital designs implemented in currently commercial available CPLDs. The test program is automatically generated from information that encompasses the design & development phase, namely: the file containing the results from simulation, the BSDL file, an internal scan chain description file, and one file containing the user options.
- An Automated Verification Process Based on Scan TechniquePublication . Alves, Gustavo R.; Krug, Margrit R.; Lubaszewski, Marcelo S.; Ferreira, Jose M.Matching the results achieved during circuit simulation with those extracted from circuit functioning is a common verification process. A large number of current verification techniques use the input / output vectors produced during functional simulation as the test vectors applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes a solution for verifying digital designs implemented in currently commercial available CPLDs. All internal flip-flops are included in a scan-chain accessible through the BST infrastructure (using a user-defined optional instruction), while the BS cells are used to apply the input test vectors and capture the circuit responses. These BS cells can either belong to the device-under-test or to other devices, the first controlled through the optional INTEST instruction and the second controlled through the mandatory EXTEST instruction. To speed up the verification process, the test program is automatically generated from information that encompasses the design & development phase.
- Remote Electronics Workbench – taking the lab homePublication . Alves, Gustavo R.; Cardoso, Antonio; Ferreira, Jose M.Students usually regard lab classes as the opportunity to practice learnt theory. Some would even pass more time in the lab performing new or the same experiment with slightly different parameters, if allowed to. Benefiting from the experience gained in the PEARL (Practical Experimentation by Accessible Remote Learning) project, the University of Porto has developed a Remote Electronics Workbench (REW) that allows students to carry out real experiments in electronics, from their home computer, through web-based access. The REW includes: interfaces to experimental scenarios; real video feedback from the lab environment; video-conference facilities to enable student-to- student and student-to-tutor dialogue; and registration and booking pages to new and registered users, respectively. It is also a constituting part of a proposal to create a Remote Experimentation Network covering both European and Latin-American countries, under the Alfa II programme.
- A Built-In Mixed-signal Block Observer (BIMBO) to improve observability in 1149.4 environmentsPublication . Felgueiras, Carlos; Alves, Gustavo R.; Ferreira, Jose M.This document proposes an extension to the IEEE 1149.4 test infrastructure [1], whereby a bank of sigma-delta first order modulators enables the simultaneous observation of several analog pins in a single component. The modulator output bit streams are shifted out and made available to an external test controller that comprises the corresponding bank of decimation filters and other decision and control logic. The architecture proposed is fully non-intrusive and may be used to support debug and test operations in mixed-signal environments.
- A self-healing real-time system based on run-time self-reconfigurationPublication . Gericota, Manuel G.; Alves, Gustavo R.; Ferreira, José M.The new generations of SRAM-based FPGA (field programmable gate array) devices are the preferred choice for the implementation of reconfigurable computing platforms intended to accelerate processing in real-time systems. However, FPGA's vulnerability to hard and soft errors is a major weakness to robust configurable system design. In this paper, a novel built-in self-healing (BISH) methodology, based on run-time self-reconfiguration, is proposed. A soft microprocessor core implemented in the FPGA is responsible for the management and execution of all the BISH procedures. Fault detection and diagnosis is followed by repairing actions, taking advantage of the dynamic reconfiguration features offered by new FPGA families. Meanwhile, modular redundancy assures that the system still works correctly