Browsing by Author "Yomsi, Patrick Meumeu"
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- Energy-aware task mapping onto heterogeneous platforms using DVFS and sleep statesPublication . Awan, Muhammad Ali; Yomsi, Patrick Meumeu; Nelissen, Geoffrey; Petters, Stefan M.Heterogeneous multicore platforms are becoming an interesting alternative for embedded computing systems with limited power supply as they can execute specific tasks in an efficient manner. Nonetheless, one of the main challenges of such platforms consists of optimising the energy consumption in the presence of temporal constraints. This paper addresses the problem of task-to-core allocation onto heterogeneous multicore platforms such that the overall energy consumption of the system is minimised. To this end, we propose a two-phase approach that considers both dynamic and leakage energy consumption: (i) the first phase allocates tasks to the cores such that the dynamic energy consumption is reduced; (ii) the second phase refines the allocation performed in the first phase in order to achieve better sleep states by trading off the dynamic energy consumption with the reduction in leakage energy consumption. This hybrid approach considers core frequency set-points, tasks energy consumption and sleep states of the cores to reduce the energy consumption of the system. Major value has been placed on a realistic power model which increases the practical relevance of the proposed approach. Finally, extensive simulations have been carried out to demonstrate the effectiveness of the proposed algorithm. In the best-case, savings up to 18% of energy are reached over the first fit algorithm, which has shown, in previous works, to perform better than other bin-packing heuristics for the target heterogeneous multicore platform.
- Methodologies for the WCET Analysis of Parallel Applications on Many-core ArchitecturesPublication . Nélis, Vincent; Yomsi, Patrick Meumeu; Pinho, Luís MiguelThere is an increasing eagerness to deploy and execute parallel applications on many-core infrastructures, pre- serving the time-predictability of the execution as required by real-time practices to upper-bound the response time of the embedded application. In this context, the paper discusses the application of the currently-available WCET analysis techniques and tools on such platforms and with highly parallel activities. After discussing the pros and cons of all different methodologies for WCET analysis, we introduce a new approach that is developed within the P-SOCRATES project.
- Online slack consolidation in global-EDF for energy consumption minimisationPublication . Awan, Muhammad Ali; Nelissen, Geoffrey; Yomsi, Patrick Meumeu; Petters, Stefan M.Leakage power dissipation is one of the major concerns in homogeneous multicore platforms. Therefore, individual cores on such platforms are often equipped with multiple sleep states to reduce the leakage power dissipation. With the current body of knowledge, an efficient selection of sleep states is a non-trivial problem for system designers. In this work, we propose leakage-aware energy management algorithms for homogeneous multicore platforms using a global-EDF scheduler. Global-EDF assumes that at any time instant the tasks (constituting the application) with the closest absolute deadlines are selected for execution on any core of the platform, sometimes allowing migration. Initially, individual cores are allowed to change their power states independently. This assumption is relaxed in the second algorithm and cores transition into different power states in coordination with each other. The main idea behind the proposed algorithms consists of exploiting the spare capacity available in the schedule of each core to either initiate a sleep state on this core or prolong the sleep state of cores already in a sleep state in order to minimise the leakage power dissipation. The presented algorithms have low complexity, thus making it practically feasible. Evaluations are carried out by assuming the specifications of Intel Xeon E3-1285L V4 embedded multicore processor and Freescale P5040 QorIQ Integrated Processor to demonstrate its effectiveness. In the best-case, up to 50% and 60% of the energy consumption wasted in idle intervals — i.e., when a core is not performing any execution — on Intel Xeon and Freescale P5040 platform, respectively, is saved over the baseline global-EDF schedule.
- A system model and stack for the parallelization of time-critical applications on many-core architecturesPublication . Nélis, Vincent; Yomsi, Patrick Meumeu; Pinho, Luís Miguel; Quiñones, Eduardo; Bertogna, Marko; Marongiu, Andrea; Gai, Paolo; Scordino, ClaudioMany embedded systems are subject to stringent timing requirementsthat compel them to "react" within prede_ned time bounds.The said "reaction" may be understood as simply outputting the resultsof a basic computation, but may also mean engaging in complex interactionswith the surrounding environment. Although these strict temporalrequirements advocate the use of simple and predictable hardwarearchitectures that allow for the computation of tight upper-bounds onthe software response time, meanwhile most of these embedded systemssteadily demand for more and more computational performance, whichweighs in favor of specialized, complex, and optimized multi-core andmany-core processors on which the execution of the application can beparallelized. However, it is not straightforward how event-based embeddedapplications can be structured in order to take advantage and fullyexploit the parallelization opportunities and achieve higher performanceand energy-e_fficient computing. The P-SOCRATES project envisions thenecessity to bring together next-generation many-core accelerators fromthe embedded computing domain with the programming models andtechniques from the high-performance computing domain, supportingthis with real-time methodologies to provide timing predictability. This paper gives an overview of the system model and software stackproposed in the P-SOCRATES project to facilitate the deployment andexecution of parallel applications on many-core infrastructures, whilepreserving the time-predictability of the execution required by real-timepractices to upper-bound the response time of the embedded application.
- The P-SOCRATES timing analysis methodology for parallel real-time applications deployed on many-core platformsPublication . Nélis, Vincent; Yomsi, Patrick Meumeu; Pinho, Luís MiguelThis paper presents the timing analysis methodology developed in the European project P-SOCRATES (Parallel Software Framework for Time-Critical Many-core Systems). This timing analysis methodology is defined for parallel applications that must satisfy b both performance and real-time requirements and are executed on modern many-core processor architectures. We discuss the motivation and objectives of the project, the timing analysis flow that we proposed, the tool that has been developed to automatize it, and finally we report on some of the preliminary results that we have obtained when applying this methodology to the three application use -cases of the project.
- Towards Certifiable Multicore-based Platforms for AvionicsPublication . Awan, Muhammad Ali; Yomsi, Patrick Meumeu; Bletsas, Konstantinos; Nélis, Vincent; Tovar, Eduardo; Souto, PedroThe demand for extra functionality in modern applications is a never ending trend. The hardware vendors are actively improving the design of processors to accommodate these complex applications. The increase in clock speed to enhance the performance of the processor has hit its limits. This is driven by the fact that the performance per watt became costly at high frequencies. Hence, Moore’s law is no longer sustained with increasing frequencies but with additional cores [1]. Therefore, in the last decade, the semiconductor industry has experienced a paradigm shift from single processor design to multicore processors (MCP). Cores in MCP share many resources like caches, main memory, I/O devices and interconnects. This sharing, which does not exist in single core processors, makes the temporal behavior of MCPs rather complex and highly unpredictable as these platforms are designed to improve the average-case performance. Consequently, their use in safetycritical applications such as avionics domain is extremely challenging. The certification authorities are very skeptical in the use of MCP platforms in avionics applications
- Towards the Certification of Multicore Platforms in the Avionics DomainPublication . Awan, Ali Awan; Yomsi, Patrick Meumeu; Bletsas, Konstantinos; Nélis, Vincent; Tovar, Eduardo; Souto, Pedron the last decade, the semiconductor industry has experienced a paradigm shift from single core design to a multicore architecture era. This trend is driven by the fact that the increase in clock speed to enhance the performance of a core has hit a limit as the performance per watt became costly at high frequencies. A multicore processor (MCP) combines two or more cores into a single package (single or multiple dies) such that they can execute programs simultaneously. Although this feature is very appealing, it comes with new challenges, unfortunately. Most MCP platforms present many sources of unpredictability as the large majority of hardware vendors are mainly interested by improving the average performance of the system. This work discusses some sources of non-determinism and highlights the envisioned methodology to mitigate or eliminate their effect in the context of safety critical systems.
- Worst-Case Communication Delay Analysis for NoC-Based Many-Cores Using a Limited Migrative ModelPublication . Nikolic, Borislav; Yomsi, Patrick Meumeu; Petters, Stefan M.A steady increase in the number of cores within many-core platforms causes increasing contentions for the interconnect medium and leads to non-negligible latencies of the inter-core communication. In order to study the worst-case execution times of applications, it is no longer sufficient to only take into account their schedulability requirements, but the communication delays also have to be considered. In this work, we focus on the worst-case communication delays of applications, deployed upon a NoC-based many-core platform using a Limited Migrative Model (LMM). The LMM approach is based on the multi-kernel paradigm, which is a promising step towards scalable and predictable many-cores. The contribution of this work is threefold. First, we extend LMM by allowing the inter-application communication, and subsequently adapt the existing method for the worst-case communication delay analysis, so as to make it applicable to the enhanced model. Then, we propose a novel method. Finally, we compare these two approaches. The experiments show that the new technique renders tighter upper-bound estimates in more than 90 % of the cases, and also demonstrates a comparable runtime performance.