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- Response time analysis of multiframe mixed-criticality systems with arbitrary deadlinesPublication . Hussain, Ishfaq; Awan, Muhammad Ali; Souto, Pedro; Bletsas, Konstantinos; Akesson, Benny; Tovar, EduardoThe well-known model of Vestal aims to avoid excessive pessimism in the quantifcation of the processing requirements of mixed-criticality systems, while still guaranteeing the timeliness of higher-criticality functions. This can bring important savings in system costs, and indirectly help meet size, weight and power constraints. This efciency is promoted via the use of multiple worst-case execution time (WCET) estimates for the same task, with each such estimate characterized by a confdence associated with a diferent criticality level. However, even this approach can be very pessimistic when the WCET of successive instances of the same task can vary greatly according to a known pattern, as in MP3 and MPEG codecs or the processing of ADVB video streams. In this paper, we present a schedulability analysis for the new multiframe mixed-criticality model, which allows tasks to have multiple, periodically repeating, WCETs in the same mode of operation. Our work extends both the analysis techniques for Static Mixed-Criticality scheduling (SMC) and Adaptive Mixed-Criticality scheduling (AMC), on one hand, and the schedulability analysis for multiframe task systems on the other. A constrained-deadline model is initially targeted, and then extended to the more general, but also more complex, arbitrary-deadline scenario. The corresponding optimal priority assignment for our schedulability analysis is also identifed. Our proposed worst-case response time (WCRT) analysis for multiframe mixed-criticality systems is considerably less pessimistic than applying the static and adaptive mixed-criticality scheduling tests oblivious to the WCET variation patterns. Experimental evaluation with synthetic task sets demonstrates up to 20% and 31.4% higher scheduling success ratio (in absolute terms) for constrained-deadline analyses and arbitrary-deadline analyses, respectively, when compared to the best of their corresponding frame-oblivious tests.
- Memory Bandwidth Regulation for Multiframe Task SetsPublication . Ali Awan, Muhammad; Souto, Pedro; Bletsas, Konstantinos; Åkesson, Benny; Tovar, EduardoTiming analysis of safety-critical real-time embedded systems should be free of both optimistic and pessimistic aspects. The multiframe model was devised to eliminate the pessimism in the schedulability analysis of systems with tasks whose worst-case execution times vary from job to job, according to known patterns. However, this model is optimistic and unsafe for multicores with shared memory controllers, since it ignores memory contention, and existing approaches to stall analysis based on memory regulation are very pessimistic if straightforwardly applied. This paper remedies this by adapting existing stall analyses for memory-regulated systems of conventional Liu-and-Layland tasks to the multiframe model. Experimental evaluations with synthetic task sets (and different task and memory budget assignment heuristics) show up to 85% higher scheduling success ratio for our analysis, compared to the frameagnostic analysis, enabling higher platform utilisation without compromising safety. We also explore implementation aspects, such as how to speed up the analysis and how to trade off accuracy with tractability.
- Schedulability analysis for CAN bus messages of periodically-varying sizePublication . Hussain, Ishfaq; Souto, Pedro; Bletsas, Konstantinos; Awan, Muhammad Ali; Tovar, EduardoConventional CAN bus schedulability analysis assumes that all messages with a given identifier have the same worst-case length. In this paper we extend that analysis to a more general model in which messages with a given identifier may have different lengths, that vary according to a known periodic pattern.That is, for some positive integer S, we assume that the length of message instances n and n + S with the same id is the same. By leveraging such patterns, where present, our new analysis allows for a more efficient use of CAN bus bandwidth than the application of conventional analysis, which can be pessimistic. This may be interesting when a given node sends the values of multiple signals with different periods. In such a scenario, the conventional CAN schedulability analysis would require either the use of different ids for different signals (assuming there are enough of them), which leads to a higher bandwidth overhead because of the reduplication of message headers, or using only one id, but pessimistically always assuming the maximum possible length of the message, for safety reasons.
- Cache-aware Schedulability Analysis of PREM Compliant TasksPublication . Rashid, Syed Aftab; Awan, Muhammad Ali; Souto, Pedro; Bletsas, Konstantinos; Tovar, EduardoThe Predictable Execution Model (PREM) is useful for mitigating inter-core interference due to shared resources such as the main memory. However, it is cache-agnostic, which makes schedulabulity analysis pessimistic, via overestimation of prefetches and write-backs. In response, we present cache-aware schedulability analysis for PREM tasks on fixed-task-priority partitioned multicores, that bounds the number of cache prefetches and write-backs. Our approach identifies memory blocks loaded in the execution of a previous scheduling interval of each task, that remain in the cache until its next scheduling interval. Doing so, greatly reduces the estimated prefetches and write backs. In experimental evaluations, our analysis improves the schedulability of PREM tasks by up to 55 percentage points.
- Response time analysis of memory-bandwidth- regulated multiframe mixed-criticality systemsPublication . Hussain, Ishfaq; Awan, Muhammad Ali; Souto, Pedro; Bletsas, Konstantinos; Tovar, EduardoThe multiframe mixed-criticality task model eliminates the pessimism in many systems where the worst-case execution times (WCETs) of successive jobs vary greatly by design, in a known pattern. Existing feasibility analysis techniques for multiframe mixed-criticality tasks are shared-resource-oblivious, hence un-safe for commercial-o -the-shelf (COTS) multicore platforms with a memory controller shared among all cores. Conversely, the feasibility analyses that account for the interference on shared resource(s) in COTS platforms do not leverage theWCET variation in multiframe tasks. This paper extends the state-of-the-art by presenting analysis that incorporates the memory access stall in memory-bandwidth-regulated multiframe mixed-criticality multicore systems. An exhaustive enumeration approach is proposed for this analysis to further enhance the schedulability success ratio. The running time of the exhaustive analysis is improved by proposing a pruning mechanism that eliminates the combinations of interfering job sequences that subsume others. Experimental evaluation, using synthetic task sets, demonstrates up to 72% improvement in terms of schedulability success ratio, compared to frame-agnostic analysis.
- Uneven memory regulation for scheduling IMA applications on multi-core platformsPublication . Awan, Muhammad Ali; Souto, Pedro; Åkesson, Benny; Bletsas, Konstantinos; Tovar, EduardoThe adoption of multi-cores for mixed-criticality systems has fueled research on techniques for providing scheduling isolation guarantees to applications of different criticalities. These are especially hard to provide in the presence of contention in shared resources of the system, such as buses and DRAMs. The state-of-the-art Single-Core Equivalence (SCE) framework improves timing isolation by enforcing periodic memory access budgets per core, which allows computing safe stall delays for the cores as input to the schedulability analysis. In this work, we extend the theoretical toolkit for this state-of-the-art framework by considering EDF and server-based scheduling, instead of partitioned fixed-priority scheduling which SCE has assumed so far. A second extension to the theory of SCE consists in additionally allowing memory access budgets to be uneven and defined on a per-server basis, rather than just on a per-core basis, which is what was supported until now. This added flexibility allows better memory bandwidth efficiency, especially when servers with dissimilar memory access requirements co-exist on a given core, and this in turn improves schedulability. Finally, we also formulate an Integer-Linear Programming Model (ILP) guaranteed to find a feasible mapping of a given set of servers to processors, including their execution time and memory access budgets, if such a mapping exists. Our experiments with synthetic task sets confirm that considerable improvement in schedulability can result from the use of per-server memory access budgets under the SCE framework.