ISEP – CIETI – Comunicações em eventos científicos
Permanent URI for this collection
Browse
Browsing ISEP – CIETI – Comunicações em eventos científicos by Subject "1149.1"
Now showing 1 - 3 of 3
Results Per Page
Sort Options
- An Automated Verification Process Based on Scan TechniquePublication . Alves, Gustavo R.; Krug, Margrit R.; Lubaszewski, Marcelo S.; Ferreira, Jose M.Matching the results achieved during circuit simulation with those extracted from circuit functioning is a common verification process. A large number of current verification techniques use the input / output vectors produced during functional simulation as the test vectors applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes a solution for verifying digital designs implemented in currently commercial available CPLDs. All internal flip-flops are included in a scan-chain accessible through the BST infrastructure (using a user-defined optional instruction), while the BS cells are used to apply the input test vectors and capture the circuit responses. These BS cells can either belong to the device-under-test or to other devices, the first controlled through the optional INTEST instruction and the second controlled through the mandatory EXTEST instruction. To speed up the verification process, the test program is automatically generated from information that encompasses the design & development phase.
- From Circuit Simulation to Circuit Verification: An Internal + Boundary Scan-based SolutionPublication . Alves, Gustavo R.; Krug, Margrit R.; Lubaszewski, Marcelo; Ferreira, Jose M.Matching the results obtained from circuit simulation with those extracted from circuit functioning is a common stage of the final verification process. Many current verification techniques use the I/O vectors produced during functional and / or timing simulation, for creating the test vectors to be applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes such a solution for verifying digital designs implemented in currently commercial available CPLDs. The test program is automatically generated from information that encompasses the design & development phase, namely: the file containing the results from simulation, the BSDL file, an internal scan chain description file, and one file containing the user options.
- Projeto para o Teste e Depuração com Base nas Arquiteturas IEEE 1149.1 e 1149.4Publication . Alves, Gustavo R.; Ferreira, José M.A infraestrutura Boundary Scan Test (BST), definida na norma IEEE 1149.1, tem sido tradicionalmente utilizada para o teste estrutural de Cartas de Circuito Impresso (CCI) na fase de produção. O seu aparecimento deveu-se, entre outras razões, à crescente dificuldade das tradicionais tecnologias de teste de CCI (o teste in-circuit e o teste funcional) em lidar com os novos tipos de encapsulamento de Circuitos Integrados (CI) e com a sua crescente complexidade. A utilização de CI de montagem superficial veio reduzir o distanciamento entre os pinos e permitir a montagem de componentes em ambos os lados da CCI, dificultando assim o acesso físico requerido pelo teste in- circuit. A crescente complexidade veio por sua vez dificultar a propagação de valores no interior da CCI, diminuindo assim a qualidade do teste funcional.