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Advisor(s)
Abstract(s)
This paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: 2-to-1 multiplexer, one-bit full adder, four-bit parity checker and a two-bit multiplier. The objective of this work is to generate a functional circuit with the minium number of gates.
Description
Keywords
Circuit design Combinational circuits Genetic algorithms Computer-aided design
