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Improved memory contention analysis for the 3-Phase task model

2024Conference object Restricted access
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dc.contributor.authorArora, Jatin
dc.contributor.authorRashid, Syed Aftab
dc.contributor.authorNelissen, Geoffrey
dc.contributor.authorMaia, Cláudio
dc.contributor.authorTovar, Eduardo
dc.date.accessioned2024-09-09T14:52:14Z
dc.date.available2024-09-09T14:52:14Z
dc.date.issued2024
dc.descriptionThis work is supported by the European Union/Next Generation EU, through the Recovery and Resilience Plan (PRR) [Project Route 25 with Nr. C645463824-00000063]. This work was also supported by the CISTER Research Unit (UIDP/UIDB/04234/2020), financed by National Funds through FCT/MCTES (Portuguese Foundation for Science and Technology).pt_PT
dc.description.abstractIn multiprocessor-based real-time systems, main memory is identified as a major bottleneck in the worst-case timing analysis of tasks. Phased execution models such as the 3-phase task model, i.e., that divides the execution of tasks into distinct computation and memory phases, have shown to be a good candidate to tackle the memory contention problem. The 3-phase execution model in particular has gained much attention from both academia and industry as it limits when tasks can access main memory to pre-defined phases. Information on when those phases may happen and their length can then be leveraged to build a fine-grained memory contention analysis. However, the existing work that focus on the memory contention analysis for 3-phase tasks may overestimate the memory contention caused by interfering write requests. This yields pessimistic bounds on the total memory contention suffered by tasks which in turn leads to pessimistic worst-case execution time (WCET) and worst-case response time (WCRT) bounds. In this work, we improve the state-of-the-art memory contention analysis for 3-phase tasks by (i) tightly bounding the memory contention that can be suffered due to write requests; and (ii) providing a new memory contention-aware WCET analysis.pt_PT
dc.description.versionN/Apt_PT
dc.identifier.citationArora, J., Rashid, S.A., Nilessen, G., Maia, C. & Tovar, E. (2024, Agust 21-23). Improved memory contention analysis for the 3-Phase task model [Conference paper]. RTCSA 2034 - 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Application, Sokcho, South Koreapt_PT
dc.identifier.urihttp://hdl.handle.net/10400.22/25941
dc.language.isoengpt_PT
dc.peerreviewedyespt_PT
dc.titleImproved memory contention analysis for the 3-Phase task modelpt_PT
dc.typeconference object
dspace.entity.typePublication
oaire.citation.conferencePlaceSokcho, South Koreapt_PT
oaire.citation.titleRTCSA 2034 - 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Applicationpt_PT
person.familyNameArora
person.familyNameNelissen
person.familyNameMaia
person.familyNameTovar
person.givenNameJatin
person.givenNameGeoffrey
person.givenNameCláudio Roberto Ribeiro
person.givenNameEduardo
person.identifier.ciencia-id8816-61C3-8763
person.identifier.ciencia-idE51E-C723-0D77
person.identifier.ciencia-idEC13-23BF-2018
person.identifier.ciencia-id6017-8881-11E8
person.identifier.orcid0000-0001-6198-6852
person.identifier.orcid0000-0003-4141-6718
person.identifier.orcid0000-0002-6567-4271
person.identifier.orcid0000-0001-8979-3876
person.identifier.scopus-author-id41561808600
person.identifier.scopus-author-id7006312557
rcaap.rightsclosedAccesspt_PT
rcaap.typeconferenceObjectpt_PT
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relation.isAuthorOfPublicatione23673cc-6b82-4d9c-94fb-4b4fca051b0d
relation.isAuthorOfPublication382626bf-f6e8-427b-b5fa-e470b5b0fb03
relation.isAuthorOfPublication80b63d8a-2e6d-484e-af3c-55849d0cb65e
relation.isAuthorOfPublication.latestForDiscoverye23673cc-6b82-4d9c-94fb-4b4fca051b0d

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