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Advisor(s)
Abstract(s)
In multiprocessor-based real-time systems, main memory is identified as a major bottleneck in the worst-case timing analysis of tasks. Phased execution models such as the 3-phase task model, i.e., that divides the execution of tasks into distinct computation and memory phases, have shown to be a good candidate to tackle the memory contention problem. The 3-phase execution model in particular has gained much attention from both academia and industry as it limits when tasks can access main memory to pre-defined phases. Information on when those phases may happen and their length can then be leveraged to build a fine-grained memory contention analysis. However, the existing work that focus on the memory contention analysis for 3-phase tasks may overestimate the memory contention caused by interfering write requests. This yields pessimistic bounds on the total memory contention suffered by tasks which in turn leads to pessimistic worst-case execution time (WCET) and worst-case response time (WCRT) bounds. In this work, we improve the state-of-the-art memory contention analysis for 3-phase tasks by (i) tightly bounding the memory contention that can be suffered due to write requests; and (ii) providing a new memory contention-aware WCET analysis.
Description
This work is supported by the European Union/Next Generation EU, through the Recovery and Resilience Plan
(PRR) [Project Route 25 with Nr. C645463824-00000063]. This work was also supported by the CISTER Research Unit (UIDP/UIDB/04234/2020), financed by National Funds through FCT/MCTES (Portuguese Foundation for Science and Technology).
Keywords
Citation
Arora, J., Rashid, S.A., Nilessen, G., Maia, C. & Tovar, E. (2024, Agust 21-23). Improved memory contention analysis for the 3-Phase task model [Conference paper]. RTCSA 2034 - 30th IEEE International Conference on Embedded and Real-Time Computing Systems and Application, Sokcho, South Korea