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Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)

dc.contributor.authorAwan, Muhammad Ali
dc.contributor.authorSouto, Pedro
dc.contributor.authorBletsas, Konstantinos
dc.contributor.authorÅkesson, Benny
dc.contributor.authorTovar, Eduardo
dc.date.accessioned2019-01-04T15:19:50Z
dc.date.available2019-01-04T15:19:50Z
dc.date.issued2018
dc.description.abstractThis artifact demonstrates the performance of the proposed worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. The memory stall analysis is implemented in Java along with five different stall-cognisant bandwidth-to-core and task-to-core assignment heuristics. It evaluates the performance of these heuristics in terms of schedulability via experiments with synthetic task sets capturing different system characteristics. It also quantifies the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers on the given multicore platform.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.doi10.4230/DARTS.4.2.5pt_PT
dc.identifier.issn2509-8195
dc.identifier.urihttp://hdl.handle.net/10400.22/12541
dc.language.isoengpt_PT
dc.peerreviewedyespt_PT
dc.publisherSchloss Dagstuhl--Leibniz-Zentrum fuer Informatikpt_PT
dc.relation.publisherversionhttp://drops.dagstuhl.de/opus/volltexte/2018/8973/pt_PT
dc.subjectMultiple memory controllerspt_PT
dc.subjectMemory regulationpt_PT
dc.subjectMulticorept_PT
dc.titleWorst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)pt_PT
dc.typejournal article
dspace.entity.typePublication
oaire.citation.endPage5:3pt_PT
oaire.citation.issue2pt_PT
oaire.citation.startPage5:1pt_PT
oaire.citation.titleDagstuhl Artifacts Seriespt_PT
oaire.citation.volume4pt_PT
person.familyNameTovar
person.givenNameEduardo
person.identifier.ciencia-id6017-8881-11E8
person.identifier.orcid0000-0001-8979-3876
person.identifier.scopus-author-id7006312557
rcaap.rightsopenAccesspt_PT
rcaap.typearticlept_PT
relation.isAuthorOfPublication80b63d8a-2e6d-484e-af3c-55849d0cb65e
relation.isAuthorOfPublication.latestForDiscovery80b63d8a-2e6d-484e-af3c-55849d0cb65e

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