A carregar...
Publicação
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact)
| Nome: | Descrição: | Tamanho: | Formato: | |
|---|---|---|---|---|
| 166.69 KB | Adobe PDF |
Orientador(es)
Resumo(s)
This artifact demonstrates the performance of the proposed worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. The memory stall analysis is implemented in Java along with five different stall-cognisant bandwidth-to-core and task-to-core assignment heuristics. It evaluates the performance of these heuristics in terms of schedulability via experiments with synthetic task sets capturing different system characteristics. It also quantifies the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers on the given multicore platform.
Descrição
Palavras-chave
Multiple memory controllers Memory regulation Multicore
Contexto Educativo
Citação
Editora
Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik