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Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures

dc.contributor.authorCasini, Daniel
dc.contributor.authorBiondi, Alessandro
dc.contributor.authorNelissen, Geoffrey
dc.contributor.authorButtazzo, Giorgio
dc.date.accessioned2019-02-07T16:40:11Z
dc.date.available2019-02-07T16:40:11Z
dc.date.issued2018
dc.description.abstractThis work proposes solutions for bounding the worst-case memory space requirement for parallel tasks running on multicore platforms with scratchpad memories. It introduces a feasibility test that verifies whether memories are large enough to contain the maximum memory backlog that may be generated by the system. Both closed-form bounds and more accurate algorithmic techniques are proposed. It is shown how one can use max-plus algebra and solutions to the max-flow cut problem to efficiently solve the memory feasibility problem. Experimental results are presented to evaluate the efficiency of the proposed feasibility analysis techniques on synthetic workload and state-of-the-art benchmarks.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.doi10.1109/RTSS.2018.00047pt_PT
dc.identifier.issn2576-3172
dc.identifier.urihttp://hdl.handle.net/10400.22/12864
dc.language.isoengpt_PT
dc.peerreviewedyespt_PT
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8603223pt_PT
dc.subjectReal-timept_PT
dc.subjectMemory feasibilitypt_PT
dc.subjectParallel taskspt_PT
dc.subjectScratchpad memoriespt_PT
dc.titleMemory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architecturespt_PT
dc.typeconference object
dspace.entity.typePublication
oaire.citation.conferencePlaceNashville, U.S.A.pt_PT
oaire.citation.endPage324pt_PT
oaire.citation.startPage312pt_PT
oaire.citation.title2018 IEEE Real-Time Systems Symposium (RTSS)pt_PT
rcaap.rightsopenAccesspt_PT
rcaap.typeconferenceObjectpt_PT

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