Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures

Casini, Daniel; Biondi, Alessandro; Nelissen, Geoffrey; Buttazzo, Giorgio

http://hdl.handle.net/10400.22/12864

Use this identifier to reference this record.

Name:	Description:	Size:	Format:
COM_CISTER_Casini_2018.pdf		687.04 KB	Adobe PDF	Download

Send Feedback

Authors

Abstract(s)

This work proposes solutions for bounding the worst-case memory space requirement for parallel tasks running on multicore platforms with scratchpad memories. It introduces a feasibility test that verifies whether memories are large enough to contain the maximum memory backlog that may be generated by the system. Both closed-form bounds and more accurate algorithmic techniques are proposed. It is shown how one can use max-plus algebra and solutions to the max-flow cut problem to efficiently solve the memory feasibility problem. Experimental results are presented to evaluate the efficiency of the proposed feasibility analysis techniques on synthetic workload and state-of-the-art benchmarks.

Keywords

Real-time Memory feasibility Parallel tasks Scratchpad memories

URI

http://hdl.handle.net/10400.22/12864

DOI

10.1109/RTSS.2018.00047

Collections

ISEP – CISTER – Comunicações em eventos científicos

Altmetrics

Full item page