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ISEP – CISTER – Comunicações em eventos científicos

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http://hdl.handle.net/10400.22/196

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Browsing ISEP – CISTER – Comunicações em eventos científicos by Subject "Access protocols"

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  • Hardware/Software Implementation Factors Influencing Ethernet Latency
    Publication . Corrêa, Tomás P.; Almeida, Luis; Bueno Peña, Emilio
    Minimum Cycle Time is a common performance indicator adopted to compare Real-Time Ethernet protocols. Though serving its purpose, Minimum Cycle Time excludes the delays inside the sending and receiving nodes, so it is insufficient to estimate the end-to-end latency. In this work, we describe some implementation possibilities of an Ethernet node in a System-on-Chip and present measurements of the delay to send/receive packets from/to the application layer. We chose different points in the software to make the measurement, so the results cover more use-cases. We found the Ethernet Lite Media Access Controller (MAC) to be faster than the hard MAC (GEM) and the Lightweight IP stack to add less than 2.2 μs. Finally, we show how a hardware accelerator can reduce the delay of high-priority packets by 1.4 μs.
    2018Conference object Restricted access Show more
  • Tightening Up Security In Low Power Deterministic Networks
    Publication . Tiberti, Walter; Vieira, Bruno; Kurunathan, John Harrison; Severino, Ricardo; Tovar, Eduardo
    The unprecedented pervasiveness of IoT systems is pushing this technology into increasingly stringent domains. Such application scenarios become even more challenging due to the demand for encompassing the interplay between safety and security. The IEEE 802.15.4 DSME MAC behavior aims at addressing such systems by providing additional deterministic, synchronous multi-channel access support. However, despite the several improvements over the previous versions of the protocol, the standard lacks a complete solution to secure communications. In this front, we propose the integration of TAKS, an hybrid cryptography scheme, over a standard DSME network. In this paper, we describe the system architecture for integrating TAKS into DSME with minimum impact to the standard, and we venture into analysing the overhead of having such security solution over application delay and throughput. After a performance analysis, we learn that it is possible to achieve a minor impact of 1% to 14% on top of the expected network delay, depending on the platform used, while still guaranteeing strong security support over the DSME network.
    2020Conference object Restricted access Show more