Browsing by Author "Yomsi, Patrick"
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- Response time analysis of hard real-time tasks sharing software transactional memory data under fully partitioned schedulingPublication . Barros, António; Yomsi, Patrick; Pinho, Luís MiguelSoftware transactional memory (STM) is a synchronisation paradigm which improves the parallelism and composability of modern applications executing on a multi-core architecture. However, to abort and retry a transaction multiple times may have a negative impact on the temporal characteristics of a real-time task set. This paper addresses this issue: It provides a framework in which an upper-bound on the worst-case response time of each task is derived, assuming that tasks are scheduled by following either the Non-Preemptive During Attempt (NPDA), Non-Preemptive Until Commit (NPUC) or Stack Resource Policy for Transactional Memory (SRPTM) policy.
- Routing heuristics for load-balanced transmission in TSN-based networksPublication . Ojewale, Mubarak; Yomsi, PatrickA carefully designed routing synthesis can help system designers achieve a better load balancing in TSN-based networks and avoid congestion. To this end purpose, this work proposes two heuristics referred to as (1) LB-DRR, which aims at achieving a better load balancing and compute as much disjoint routing paths as possible for each replicated flow; and (2) CR-DRR, which recomputes paths for time-sensitive flows in congestion situations. Extensive simulations demonstrate that the proposed approach outperforms the classical Shortest Path (SPA) and the weighted Equal Cost Multi-path (wt-ECMP) algorithms in terms of the maximum load transmitted on a link by more than 70% and 20%, respectively.
- The variability of application execution times on a multi-core platformPublication . Nelis, Vincent; Yomsi, Patrick; Pinho, Luís MiguelIt is a known fact that processes running concurrently on different cores in a multicore environment interfere with each other on the processor shared resources. The contention on these shared resources considerably slows down the execution on every core since sometimes the cores must stall while their requests to access the resources are being served. But by how much the execution may b e s lowed down due to this interference? In this pap er we answer this question with numbers coming from experimentation. That is, we quantify the magnitude of the impact of the interference on the execution time by running programs taken from the TACLeBench benchmark suite, a popular benchmark suite in the real-time research community, on the first generation of Kalray manycore processor family, the MPPA-256 (the development board) that goes by the code name “Andey”.