Browsing by Author "Ferreira, José M."
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- An embedded 1149.4 extension to support mixed-signal debuggingPublication . Felgueiras, Carlos; Alves, Gustavo R.; Ferreira, José M.Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources providing support to that activity, first at the printed circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However, all these developments had a small impact in the analog and mixed-signal domain, where debugging still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated with debugging increase, which cause the time-to-market and the prototype verification costs to also increase. The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis operations. One of the main advantages associated with the proposed solution is the seamless migration to the system-on-chip level, as the access is done through electronic means, thus easing debugging operations at different hierarchical levels.
- An Enhanced Debugger for Real-Time Fault Injection on Microprocessor SystemsPublication . Fidalgo, André Vaz; Alves, Gustavo R.; Ferreira, José M.As electronic devices get smaller and more complex, dependability assurance is becoming fundamental for many mission critical computer based systems. This paper presents a case study on the possibility of using the on-chip debug infrastructures present in most current microprocessors to execute real time fault injection campaigns. The proposed methodology is based on a debugger, customized for fault injection and designed for maximum flexibility, and consists on injecting bit-flip type faults on memory elements without modifying or halting the target application. The proposed solution is easily portable and applicable to different architectures, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.
- An HDL Approach to Board-Level BISTPublication . Alves, Gustavo R.; Gericota, Manuel G.; Ramalho, José L.; Ferreira, José M.Boundary scan is now the most promising technology for testing high-complexity printed circuit boards. The number of BST components available to board-level designers is however still restricted, limiting the achievable fault coverage. The requirements to improve board-level testability are analysed, and a corresponding set of testability building blocks are proposed. A low-cost and maximum-flexibility solution is described, which implements these blocks on medium-complexity PLDs, using a simple and powerful HDL.
- Assessing Defragmentation Strategies for FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Lemos, Luís; Ferreira, José M.Fragmentation on dynamically reconfigurable FPGAs is currently a major obstacle to the efficient management of its logic space. When resource allocation decisions have to be made at run-time a relocation of currently running functions may be necessary to release enough contiguous resources to implement incoming functions. Relocation should have into account any specifics of function’s functionality and also those of the FPGA’s architecture as to not affect system’s performance. A simple and fast method to assess performance degradation of a function during relocation is proposed in this paper. This method is based on previous function labelling and on the new concept of proximity vectors.
- Board-level prototype validation: a built-in controller and extended BST architecturePublication . Alves, Gustavo R.; Amaral, T.; Ferreira, José M.Prototype validation is a major concern in modern electronic product design and development. Simulation, structural test, functional and timing debug are all forming parts of the validation process, although very often addressed as dissociated tasks. In this paper we describe an integrated approach to board-level prototype validation, based on a set of mandatory/optional BST instructions and a built-in controller for debug and test, that addresses the late mentioned tasks as inherent parts of a whole process
- Collaborative learning in a qeb-accessible workbenchPublication . Ferreira, José M.; Alves, Gustavo R.; Costa, Ricardo J.; Hine, NickWeb-based course management and delivery is regarded by many institutions as a key factor in an increasingly competitive education and training world, but the systems currently available are largely unsatisfactory in terms of supporting collaborative work and access to practical science facilities. These limitations are less important in areas where “pen-and-paper” courseware is the mainstream, but become unacceptably restrictive when student assignments require real-time teamwork and access to laboratory equipment. This paper presents a web-accessible workbench for electronics design and test, which was developed in the scope of an European IST project entitled PEARL, with the aim of supporting two main features: full web access and collaborative learning facilities.
- A comparative analysis of fault injection methods via enhanced on-chip debug infrastructuresPublication . Fidalgo, André Vaz; Alves, Gustavo R.; Gericota, Manuel G.; Ferreira, José M.On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.
- A framework for fault tolerant real time systems based on reconfigurable FPGAsPublication . Gericota, Manuel G.; Lemos, L. F.; Alves, Gustavo R.; Barbosa, M. M.; Ferreira, José M.To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.
- A Framework for Implementing Radiation-Tolerant Circuits on Reconfigurable FPGAsPublication . Gericota, Manuel G.; Alves, Gustavo R.; Lemos, Luis; Ferreira, José M.The outstanding versatility of SRAM-based FPGAs make them the preferred choice for implementing complex customizable circuits. To increase the amount of logic available, manufacturers are using nanometric technologies to boost logic density and reduce prices. However, the use of nanometric scales also makes FPGAs particularly vulnerable to radiation-induced faults, especially because of the increasing amount of configuration memory cells that are necessary to define their functionality. This paper describes a framework for implementing circuits immune to radiation-induced faults, based on a customized Triple Modular Redundancy (TMR) infrastructure and on a detection-and-fix controller. This controller is responsible for the detection of data incoherencies, location of the faulty module and restoration of the original configuration, without affecting the normal operation of the mission logic. A short survey of the most recent data published concerning the impact of radiation-induced faults in FPGAs is presented to support the assumptions underlying our proposed framework. A detailed explanation of the controller functionality is also provided, followed by an experimental case study.
- A framework for self-healing radiation-tolerant implementations on reconfigurable FPGAsPublication . Gericota, Manuel G.; Lemos, L. F.; Alves, Gustavo R.; Ferreira, José M.To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant implementations, based on triple modular redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of multi-bit upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established. A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.