Browsing by Author "Aftab Rashid, Syed"
Now showing 1 - 5 of 5
Results Per Page
Sort Options
- Cache Persistence-Aware Memory Bus Contention Analysis for Multicore SystemsPublication . Aftab Rashid, Syed; Nelissen, Geoffrey; Tovar, EduardoMemory bus contention strongly relates to the number of main memory requests generated by tasks running on different cores of a multicore platform, which, in turn, depends on the content of the cache memories during the execution of those tasks. Recent works have shown that due to cache persistence the memory access demand of multiple jobs of a task may not always be equal to its worst-case memory access demand in isolation. Analysis of the variable memory access demand of tasks due to cache persistence leads to significantly tighter worst-case response time (WCRT) of tasks.In this work, we show how the notion of cache persistence can be extended from single-core to multicore systems. In particular, we focus on analyzing the impact of cache persistence on the memory bus contention suffered by tasks executing on a multi-core platform considering both work conserving and non-work conserving bus arbitration policies. Experimental evaluation shows that cache persistence-aware analyses of bus arbitration policies increase the number of task sets deemed schedulable by up to 70 percentage points in comparison to their respective counterparts that do not account for cache persistence.
- ResilienceP Analysis: Bounding Cache Persistence Reload Overhead for Set-Associative CachesPublication . Aftab Rashid, SyedThis work presents different approaches to calculate CPRO for set-associative caches. The PCB-ECB approach uses PCBs of the task under analysis and ECBs of all other tasks in the system to provide sound estimates of CPRO for set-associative caches. The resilienceP analysis then removes some of the pessimism in the PCB-ECB approach by considering the resilience of PCBs during CPRO calculations. We show that using the state-of-the-art (SoA) resilience analysis to calculate resilience of PCBs may result in underestimating the CPRO tasks may suffer. Finally, we have also presented a multi-set alike resilienceP analysis that highlights the pessimism in the resilienceP analysis and provides some insights on how it can be removed.
- ResilienceP Analysis: Bounding Cache Persistence Reload Overhead for Set-Associative CachesPublication . Aftab Rashid, Syed; Nelissen, Geoffrey; Tovar, EduardoThis work presents different approaches to calculate CPRO for set-associative caches. The PCB-ECB approach uses PCBs of the task under analysis and ECBs of all other tasks in the system to provide sound estimates of CPRO for set-associative caches. The resilienceP analysis then removes some of the pessimism in the PCB-ECB approach by considering the resilience of PCBs during CPRO calculations. We show that using the state-of-the-art (SoA) resilience analysis to calculate resilience of PCBs may result in underestimating the CPRO tasks may suffer. Finally, we have also presented a multi-set alike resilienceP analysis that highlights the pessimism in the resilienceP analysis and provides some insights on how it can be removed.
- Server Based Task Allocation to Reduce Inter-Task Memory Interference in Multicore SystemsPublication . Aftab Rashid, SyedIn multicore systems tasks running on one core may experience inter-task interference from tasks running on other cores. This inter-task interference is due to contention in using shared resources such as caches, system bus and the main memory. In this work, we focus on one of the major sources of cross-core interference in multicore systems, i.e., main memory. The idea is to allocate tasks to cores in a way that the total memory demand of all tasks executing at a time instant t is less than the minimum available memory bandwidth, i.e., DRAM min. The problem is formulated as a server-to-core mapping problem where each server constitute a set of tasks corresponding to an application. As mapping problems in multicore systems are NP-hard, we use different heuristic and meta-heuristic based approaches to find a feasible solution. Results show that our approach can perform well in multicore systems with ≤ 8 processing cores with the memory demand of each server upper bounded by DRAM min/2.
- Trading Between Intra- and Inter-Task Cache Interference to Improve SchedulabilityPublication . Aftab Rashid, Syed; Nelissen, Geoffrey; Tovar, EduardoCaches help reduce the average execution time of tasks due to their fast operational speeds. However, caches may also severely degrade the timing predictability of the system due to intra- and inter-task cache interference. Intra-task cache interference occurs if the memory footprint of a task is larger than the allocated cache space or when two memory entries of that task are mapped to the same space in cache. Inter-task cache interference occurs when memory entries of two or more distinct tasks use the same cache space. State-of-the-art analysis focusing on bounding cache interference or reducing it by means of partitioning and by optimizing task layout in memory either focus on intra- or inter-task cache interference and do not exploit the fact that both intra- and inter-task cache interference can be interrelated. In this work, we show how one can model intra- and inter-task cache interference in a way that allows balancing their respective contribution to tasks worst-case response times. Since the placement of tasks in memory and their respective cache footprint determine the intra- and inter-task interference that tasks may suffer, we propose a technique based on cache coloring to improve task set schedulability. Experimental evaluations performed using Mälardalen benchmarks show that our approach results in up to 13% higher task set schedulability than state-of-the-art approaches.