Publication
Uneven memory regulation for scheduling IMA applications on multi-core platforms
| dc.contributor.author | Awan, Muhammad Ali | |
| dc.contributor.author | Souto, Pedro | |
| dc.contributor.author | Åkesson, Benny | |
| dc.contributor.author | Bletsas, Konstantinos | |
| dc.contributor.author | Tovar, Eduardo | |
| dc.date.accessioned | 2018-12-20T11:57:20Z | |
| dc.date.embargo | 2119 | |
| dc.date.issued | 2018 | |
| dc.description.abstract | The adoption of multi-cores for mixed-criticality systems has fueled research on techniques for providing scheduling isolation guarantees to applications of different criticalities. These are especially hard to provide in the presence of contention in shared resources of the system, such as buses and DRAMs. The state-of-the-art Single-Core Equivalence (SCE) framework improves timing isolation by enforcing periodic memory access budgets per core, which allows computing safe stall delays for the cores as input to the schedulability analysis. In this work, we extend the theoretical toolkit for this state-of-the-art framework by considering EDF and server-based scheduling, instead of partitioned fixed-priority scheduling which SCE has assumed so far. A second extension to the theory of SCE consists in additionally allowing memory access budgets to be uneven and defined on a per-server basis, rather than just on a per-core basis, which is what was supported until now. This added flexibility allows better memory bandwidth efficiency, especially when servers with dissimilar memory access requirements co-exist on a given core, and this in turn improves schedulability. Finally, we also formulate an Integer-Linear Programming Model (ILP) guaranteed to find a feasible mapping of a given set of servers to processors, including their execution time and memory access budgets, if such a mapping exists. Our experiments with synthetic task sets confirm that considerable improvement in schedulability can result from the use of per-server memory access budgets under the SCE framework. | pt_PT |
| dc.description.version | info:eu-repo/semantics/publishedVersion | pt_PT |
| dc.identifier.doi | 10.1007/s11241-018-9322-y | pt_PT |
| dc.identifier.issn | 0922-6443 | |
| dc.identifier.uri | http://hdl.handle.net/10400.22/12449 | |
| dc.language.iso | eng | pt_PT |
| dc.peerreviewed | yes | pt_PT |
| dc.publisher | Springer US | pt_PT |
| dc.relation.publisherversion | https://link.springer.com/article/10.1007%2Fs11241-018-9322-y | pt_PT |
| dc.subject | Safety critical systems | pt_PT |
| dc.subject | Real-time scheduling | pt_PT |
| dc.subject | IMA applications | pt_PT |
| dc.subject | Uneven memory bandwidth | pt_PT |
| dc.subject | Single core equivalence | pt_PT |
| dc.subject | Server-based scheduling | pt_PT |
| dc.title | Uneven memory regulation for scheduling IMA applications on multi-core platforms | pt_PT |
| dc.type | journal article | |
| dspace.entity.type | Publication | |
| oaire.citation.endPage | 45 | pt_PT |
| oaire.citation.startPage | 1 | pt_PT |
| oaire.citation.title | Real-Time Systems | pt_PT |
| person.familyName | Souto | |
| person.familyName | Tovar | |
| person.givenName | Pedro | |
| person.givenName | Eduardo | |
| person.identifier.ciencia-id | 3114-46AE-02BB | |
| person.identifier.ciencia-id | 6017-8881-11E8 | |
| person.identifier.orcid | 0000-0002-0822-3423 | |
| person.identifier.orcid | 0000-0001-8979-3876 | |
| person.identifier.scopus-author-id | 23398810800 | |
| person.identifier.scopus-author-id | 7006312557 | |
| rcaap.rights | closedAccess | pt_PT |
| rcaap.type | article | pt_PT |
| relation.isAuthorOfPublication | 497682b6-33c1-47fb-a02d-b18bc941093b | |
| relation.isAuthorOfPublication | 80b63d8a-2e6d-484e-af3c-55849d0cb65e | |
| relation.isAuthorOfPublication.latestForDiscovery | 80b63d8a-2e6d-484e-af3c-55849d0cb65e |