Publication
An extensible framework for multicore response time analysis
| dc.contributor.author | David, Robert I. | |
| dc.contributor.author | Altmeyer, Sebastian | |
| dc.contributor.author | Indrusiak, Leandro S. | |
| dc.contributor.author | Maiza, Claire | |
| dc.contributor.author | Nelis, Vincent | |
| dc.contributor.author | Reineke, Jan | |
| dc.date.accessioned | 2018-01-11T14:57:03Z | |
| dc.date.available | 2018-01-11T14:57:03Z | |
| dc.date.issued | 2017 | |
| dc.description.abstract | In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on context-independent WCET values. Instead, the analysis formulates response times directly from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation. | pt_PT |
| dc.description.version | info:eu-repo/semantics/publishedVersion | pt_PT |
| dc.identifier.doi | 10.1007/s11241-017-9285-4 | pt_PT |
| dc.identifier.issn | 1573-1383 | |
| dc.identifier.uri | http://hdl.handle.net/10400.22/10760 | |
| dc.language.iso | eng | pt_PT |
| dc.peerreviewed | yes | pt_PT |
| dc.publisher | Springer | pt_PT |
| dc.relation.publisherversion | https://link.springer.com/article/10.1007%2Fs11241-017-9285-4 | pt_PT |
| dc.subject | Multicore scheduling | pt_PT |
| dc.subject | Timing analysis | pt_PT |
| dc.subject | Verification | pt_PT |
| dc.title | An extensible framework for multicore response time analysis | pt_PT |
| dc.type | journal article | |
| dspace.entity.type | Publication | |
| oaire.citation.endPage | 55 | pt_PT |
| oaire.citation.startPage | 1 | pt_PT |
| oaire.citation.title | Real-Time Systems, Special issue on Real Time and Networks Systems | pt_PT |
| rcaap.rights | openAccess | pt_PT |
| rcaap.type | article | pt_PT |