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Response time analysis of memory-bandwidth- regulated multiframe mixed-criticality systems

2021-12-15Journal article Open access
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dc.contributor.authorHussain, Ishfaq
dc.contributor.authorAwan, Muhammad Ali
dc.contributor.authorSouto, Pedro
dc.contributor.authorBletsas, Konstantinos
dc.contributor.authorTovar, Eduardo
dc.date.accessioned2022-01-17T10:51:18Z
dc.date.available2022-01-17T10:51:18Z
dc.date.issued2021-12-15
dc.description.abstractThe multiframe mixed-criticality task model eliminates the pessimism in many systems where the worst-case execution times (WCETs) of successive jobs vary greatly by design, in a known pattern. Existing feasibility analysis techniques for multiframe mixed-criticality tasks are shared-resource-oblivious, hence un-safe for commercial-o -the-shelf (COTS) multicore platforms with a memory controller shared among all cores. Conversely, the feasibility analyses that account for the interference on shared resource(s) in COTS platforms do not leverage theWCET variation in multiframe tasks. This paper extends the state-of-the-art by presenting analysis that incorporates the memory access stall in memory-bandwidth-regulated multiframe mixed-criticality multicore systems. An exhaustive enumeration approach is proposed for this analysis to further enhance the schedulability success ratio. The running time of the exhaustive analysis is improved by proposing a pruning mechanism that eliminates the combinations of interfering job sequences that subsume others. Experimental evaluation, using synthetic task sets, demonstrates up to 72% improvement in terms of schedulability success ratio, compared to frame-agnostic analysis.pt_PT
dc.description.sponsorshipThis work was partially supported by National Funds through FCT/MCTES (Portuguese Foundation for Science and Technology), within the CISTER Research Unit (UIDP/UIDB/04234/2020); by the Operational Competitiveness Programme and Internationalization (COMPETE 2020) under the PT2020 Partnership Agreement, through the European Regional Development Fund (ERDF), and by national funds through the FCT, within project PREFECT (POCI01-0145-FEDER-029119); by FCT through the European Social Fund (ESF) and the Regional Operational Programme (ROP) Norte 2020, under grant 2020.08045.BD.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.doi10.1016/j.sysarc.2021.102346pt_PT
dc.identifier.urihttp://hdl.handle.net/10400.22/19530
dc.language.isoengpt_PT
dc.publisherElsevierpt_PT
dc.relationUIDP/UIDB/04234/2020pt_PT
dc.relationPOCI-01-0145-FEDER- 029119pt_PT
dc.relation2020. 08045.BD.pt_PT
dc.relation.ispartofseries211006;
dc.relation.publisherversionhttps://www.sciencedirect.com/science/article/pii/S1383762121002381#!pt_PT
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/pt_PT
dc.subjectMixed criticality systempt_PT
dc.subjectMultiframe task systemspt_PT
dc.subjectMultiprocessor system on chip (MPSoC)pt_PT
dc.subjectMemory bandwidth regulationpt_PT
dc.titleResponse time analysis of memory-bandwidth- regulated multiframe mixed-criticality systemspt_PT
dc.typejournal article
dspace.entity.typePublication
oaire.citation.titleJournal of Systems Architecturept_PT
person.familyNameHussain
person.familyNameAwan
person.familyNameSouto
person.familyNameBletsas
person.familyNameTovar
person.givenNameIshfaq
person.givenNameMuhammad Ali
person.givenNamePedro
person.givenNameKonstantinos
person.givenNameEduardo
person.identifier.ciencia-id7F16-B260-48E1
person.identifier.ciencia-id9A1C-38D6-BA2D
person.identifier.ciencia-id3114-46AE-02BB
person.identifier.ciencia-idC614-0255-0E07
person.identifier.ciencia-id6017-8881-11E8
person.identifier.orcid0000-0002-4470-1744
person.identifier.orcid0000-0001-5817-2284
person.identifier.orcid0000-0002-0822-3423
person.identifier.orcid0000-0002-3640-0239
person.identifier.orcid0000-0001-8979-3876
person.identifier.scopus-author-id23398810800
person.identifier.scopus-author-id6507950422
person.identifier.scopus-author-id7006312557
rcaap.rightsopenAccesspt_PT
rcaap.typearticlept_PT
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