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An evolutionary approach to the synthesis of combinational circuits

dc.contributor.authorReis, Cecília
dc.contributor.authorTenreiro Machado, J. A.
dc.date.accessioned2019-04-01T15:07:27Z
dc.date.available2019-04-01T15:07:27Z
dc.date.issued2003-08-29
dc.description.abstractThis paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: 2-to-1 multiplexer, one-bit full adder, four-bit parity checker and two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gates.pt_PT
dc.description.versionN/Apt_PT
dc.identifier.urihttp://hdl.handle.net/10400.22/13312
dc.language.isoengpt_PT
dc.subjectGenetic algorithmpt_PT
dc.subjectFunctional circuitpt_PT
dc.titleAn evolutionary approach to the synthesis of combinational circuitspt_PT
dc.typeconference object
dspace.entity.typePublication
oaire.citation.conferencePlaceSiófok, Hungarypt_PT
oaire.citation.endPage8pt_PT
oaire.citation.startPage1pt_PT
oaire.citation.titleIEEE International conference on computational cyberneticspt_PT
person.familyNameReis
person.familyNameTenreiro Machado
person.givenNameCecília
person.givenNameJ. A.
person.identifier.ciencia-id7A18-4935-5B29
person.identifier.orcid0000-0001-6131-4677
person.identifier.orcid0000-0003-4274-4879
person.identifier.ridM-2173-2013
person.identifier.scopus-author-id55989030100
rcaap.rightsopenAccesspt_PT
rcaap.typeconferenceObjectpt_PT
relation.isAuthorOfPublication8128af5d-07d3-4b24-944d-30fde21ae59b
relation.isAuthorOfPublication82cd5c17-07b6-492b-b3e3-ecebdad1254f
relation.isAuthorOfPublication.latestForDiscovery82cd5c17-07b6-492b-b3e3-ecebdad1254f

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