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Cache-Persistence-Aware Response-Time Analysis for Fixed-Priority Preemptive Systems

dc.contributor.authorRashid, Syed Aftab
dc.contributor.authorNelissen, Geoffrey
dc.contributor.authorHardy, Damien
dc.contributor.authorÅkesson, Benny
dc.contributor.authorPuaut, Isabelle
dc.contributor.authorTovar, Eduardo
dc.date.accessioned2017-02-03T11:26:34Z
dc.date.available2017-02-03T11:26:34Z
dc.date.issued2016
dc.description28th Euromicro Conference on Real-Time Systems (ECRTS 2016). 5 to 8, Jul, 2016. Toulouse, France.Outstanding Paper Awardpt_PT
dc.description.abstractA task can be preempted by several jobs of higher priority tasks during its response time. Assuming the worst-case memory demand for each of these jobs leads to pessimistic worstcase response time (WCRT) estimations. Indeed, there is a big chance that a large portion of the instructions and data associated with the preempting task τj are still available in the cache when τj releases its next jobs. Accounting for this observation allows the pessimism of WCRT analysis to be significantly reduced, which is not considered by existing work. The four main contributions of this paper are: 1) The concept of persistent cache blocks is introduced in the context of WCRT analysis, which allows re-use of cache blocks to be captured, 2) A cache-persistence-aware WCRT analysis for fixed-priority preemptive systems exploiting the PCBs to reduce the WCRT bound, 3) An multi-set extension of the analysis that further improves the WCRT bound, and 4) An evaluation showing that our cache-persistence-aware WCRT analysis results in up to 10% higher schedulability than state-of-the-art approaches.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.doi10.1109/ECRTS.2016.25pt_PT
dc.identifier.urihttp://hdl.handle.net/10400.22/9504
dc.language.isoengpt_PT
dc.publisherInstitute of Electrical and Electronics Engineerspt_PT
dc.relationEmbedded Multi-Core Systems for Mixed Criticality Applications in Dynamic and Changeable Real-Time Environments
dc.relationGuaranteed Component Assembly with Round Trip Analysis for Energy Efficient High-integrity Multi-core Systems
dc.relation.ispartofseriesECRTS;2016
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/7557886/pt_PT
dc.subjectStorage managementpt_PT
dc.subjectCache storagept_PT
dc.subjectEstimation theorypt_PT
dc.titleCache-Persistence-Aware Response-Time Analysis for Fixed-Priority Preemptive Systemspt_PT
dc.typeconference object
dspace.entity.typePublication
oaire.awardTitleEmbedded Multi-Core Systems for Mixed Criticality Applications in Dynamic and Changeable Real-Time Environments
oaire.awardTitleGuaranteed Component Assembly with Round Trip Analysis for Energy Efficient High-integrity Multi-core Systems
oaire.awardURIinfo:eu-repo/grantAgreement/EC/FP7/621429/EU
oaire.awardURIinfo:eu-repo/grantAgreement/EC/FP7/333053/EU
oaire.citation.conferencePlace5 to 8, Jul, 2016. Toulouse, Francept_PT
oaire.citation.title28th Euromicro Conference on Real-Time Systemspt_PT
oaire.fundingStreamFP7
oaire.fundingStreamFP7
person.familyNameTovar
person.givenNameEduardo
person.identifier.ciencia-id6017-8881-11E8
person.identifier.orcid0000-0001-8979-3876
person.identifier.scopus-author-id7006312557
project.funder.identifierhttp://doi.org/10.13039/501100008530
project.funder.identifierhttp://doi.org/10.13039/501100008530
project.funder.nameEuropean Commission
project.funder.nameEuropean Commission
rcaap.rightsclosedAccesspt_PT
rcaap.typeconferenceObjectpt_PT
relation.isAuthorOfPublication80b63d8a-2e6d-484e-af3c-55849d0cb65e
relation.isAuthorOfPublication.latestForDiscovery80b63d8a-2e6d-484e-af3c-55849d0cb65e
relation.isProjectOfPublicationc05ca6d0-eb47-46e6-93ae-3218a8c9ee48
relation.isProjectOfPublication17322fe8-c558-4180-88af-8ed0b847498c
relation.isProjectOfPublication.latestForDiscoveryc05ca6d0-eb47-46e6-93ae-3218a8c9ee48

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