Publication
Formal Verification of AADL Models Using UPPAAL
| dc.contributor.author | Gonçalves, Fernando | |
| dc.contributor.author | Pereira, David | |
| dc.contributor.author | Tovar, Eduardo | |
| dc.contributor.author | Becker, Leandro | |
| dc.date.accessioned | 2018-02-02T16:23:03Z | |
| dc.date.available | 2018-02-02T16:23:03Z | |
| dc.date.issued | 2017 | |
| dc.description | VII Brazilian Symposium on Computing Systems Engineering (SBESC 2017), Session 10: Development and Tools - B, . | pt_PT |
| dc.description.abstract | Cyber-Physical Systems (CPS) are known to be highly complex systems which can be applied to a variety of different environments, covering both civil and military application domains. As CPS are typically complex systems, its design process requires strong guarantees that the specified functional and non-functional properties are satisfied on the designed application. Model-Driven Engineering (MDE) and high-level specification languages are a valuable asset to help the design and evaluation of such complex systems. However, when looking at the existing MDE tool-support, it is observed that there is still little support for the automated integration of formal verification techniques in these tools. Given that formal verification is necessary to ensure the levels of reliability required by safety critical CPS, this paper presents an approach that aims to integrate the Model Checking technique in the CPS design process for the purpose of correctly analyzing temporal and safety characteristics. A tool named ECPS Verifier was designed to support the model checking integration into the design process, providing the generation of timed automata models from high-levels specifications in AADL. The proposed method is illustrated by means of the design of an Unmanned Aerial Vehicle, from where we derive the timed automata models to be analyzed in the UPPAAL tool. | pt_PT |
| dc.description.version | info:eu-repo/semantics/publishedVersion | pt_PT |
| dc.identifier.doi | 10.1109/SBESC.2017.22 | pt_PT |
| dc.identifier.issn | 2324-7894 | |
| dc.identifier.uri | http://hdl.handle.net/10400.22/10970 | |
| dc.language.iso | eng | pt_PT |
| dc.peerreviewed | yes | pt_PT |
| dc.publisher | Institute of Electrical and Electronics Engineers | pt_PT |
| dc.relation | EU ECSEL JU under the H2020 Framework Programme, within project ECSEL/0006/2015, JU grant nr. 692455-2 (ENABLE-S3). | pt_PT |
| dc.relation.ispartofseries | SBESC;2017 | |
| dc.relation.publisherversion | http://ieeexplore.ieee.org/document/8116568/ | pt_PT |
| dc.title | Formal Verification of AADL Models Using UPPAAL | pt_PT |
| dc.type | conference object | |
| dspace.entity.type | Publication | |
| oaire.citation.conferencePlace | Curitiba, Brasil | pt_PT |
| oaire.citation.endPage | 124 | pt_PT |
| oaire.citation.startPage | 117 | pt_PT |
| oaire.citation.title | Computing Systems Engineering (SBESC), 2017 VII Brazilian Symposium on | pt_PT |
| person.familyName | Tovar | |
| person.givenName | Eduardo | |
| person.identifier.ciencia-id | 6017-8881-11E8 | |
| person.identifier.orcid | 0000-0001-8979-3876 | |
| person.identifier.scopus-author-id | 7006312557 | |
| rcaap.rights | openAccess | pt_PT |
| rcaap.type | conferenceObject | pt_PT |
| relation.isAuthorOfPublication | 80b63d8a-2e6d-484e-af3c-55849d0cb65e | |
| relation.isAuthorOfPublication.latestForDiscovery | 80b63d8a-2e6d-484e-af3c-55849d0cb65e |