Synthesis of combinational logic circuits using genetic algorithms

Reis, Cecília; Tenreiro Machado, J. A.

http://hdl.handle.net/10400.22/13322

Use this identifier to reference this record.

Name:	Description:	Size:	Format:
COM_MachadoTenreiro138.pdf		1.26 MB	Adobe PDF	Download

Send Feedback

Authors

Reis, Cecília

Tenreiro Machado, J. A.

Abstract(s)

This paper proposes a genetic algorithm for designing combinational logic circuits and studies three different case examples: the one-bit full adder, the four-bit parity checker and the two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gates.