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Synthesis of combinational logic circuits using genetic algorithms
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Orientador(es)
Resumo(s)
This paper proposes a genetic algorithm for designing combinational logic circuits and studies three different case examples: the one-bit full adder, the four-bit parity checker and the two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gates.
Descrição
Palavras-chave
Circuit design Combinational circuits Genetic algorithms Computer-aided design