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Advisor(s)
Abstract(s)
The IEEE 1149.4 Standard for a Mixed-Signal (MS)
Test Bus proposes an extension to the well-accepted IEEE 1149.1
boundary-scan test architecture, with the objective of facilitating
interconnect, parametric and internal testing of MS circuits. An
Analog Test Access Port (ATAP) comprising two pins called AT1
and AT2, and an internal analog bus (AB) comprising two lines
(AB1, AB2), enable analog test stimulae and responses to be
routed to any pin possessing an Analog Boundary Module (ABMs
replace the IEEE 1149.1 test cells in the case of analog pins). A
Test Bus Interface Circuit (TBIC) comprising ten analog
switches defines how the ATAP and the internal analog bus are
(dis)connected, and the six analog switches in each ABM define
what connections should be established between the pin, the core
circuitry, and the internal analog bus. The large number of
analog switches in the 1149.4 test architecture may raise
concerns about their integrity, particularly when they are used
frequently, as would be the case in an 1149.4-based MS debug
strategy. This paper proposes a set of integrity check procedures
that address only the 1149.4 extensions: ATAP, TBIC, AB lines,
ABMs.
Description
Keywords
IEEE1149.4 Integrity Verification