Publication
A Framework for System-level co-verification using the BST infrastructure
| dc.contributor.author | Alves, Gustavo R. | |
| dc.contributor.author | Amaral, Telmo | |
| dc.contributor.author | Ferreira, José M. | |
| dc.date.accessioned | 2017-03-29T10:16:16Z | |
| dc.date.available | 2017-03-29T10:16:16Z | |
| dc.date.issued | 1999 | |
| dc.description.abstract | A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts. | pt_PT |
| dc.description.version | info:eu-repo/semantics/publishedVersion | pt_PT |
| dc.identifier.uri | http://hdl.handle.net/10400.22/9733 | |
| dc.language.iso | eng | pt_PT |
| dc.relation.ispartofseries | DATE'99; | |
| dc.subject | FPGAs | pt_PT |
| dc.subject | Boundary Scan Test | pt_PT |
| dc.title | A Framework for System-level co-verification using the BST infrastructure | pt_PT |
| dc.type | conference object | |
| dspace.entity.type | Publication | |
| oaire.citation.conferencePlace | Munique, Alemanha | pt_PT |
| oaire.citation.title | User ́s Forum in Design, Automation and Test in Europe (DATE’99) | pt_PT |
| person.familyName | Alves | |
| person.givenName | Gustavo | |
| person.identifier | 150015 | |
| person.identifier.ciencia-id | 4210-4DF2-5206 | |
| person.identifier.orcid | 0000-0002-1244-8502 | |
| person.identifier.rid | I-7876-2014 | |
| person.identifier.scopus-author-id | 7006053908 | |
| rcaap.rights | openAccess | pt_PT |
| rcaap.type | conferenceObject | pt_PT |
| relation.isAuthorOfPublication | 01800568-7eaf-41d9-b78d-cf64f7c7381d | |
| relation.isAuthorOfPublication.latestForDiscovery | 01800568-7eaf-41d9-b78d-cf64f7c7381d |