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A Framework for System-level co-verification using the BST infrastructure
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Orientador(es)
Resumo(s)
A good verification strategy should bring near the
simulation and real functioning environments. In
this paper we describe a system-level co-verification
strategy that uses a common flow for functional
simulation, timing simulation and functional debug.
This last step requires using a BST infrastructure,
now widely available on commercial devices,
specially on FPGAs with medium/large pin-counts.
Descrição
Palavras-chave
FPGAs Boundary Scan Test