A Framework for System-level co-verification using the BST infrastructure

Alves, Gustavo R.; Amaral, Telmo; Ferreira, José M.

http://hdl.handle.net/10400.22/9733

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Authors

Alves, Gustavo R.

Amaral, Telmo

Ferreira, José M.

Abstract(s)

A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.