Airborne data collection on resilient system architectures

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Publications

Complex Intersections with a Dedicated Road Lane per Crossing Direction

Publication . Reddy, Radha; Almeida, Luis; Santos, Pedro M.; Tovar, Eduardo

Complex intersections are often busier with a separate road lane per crossing direction, i.e., left, straight, and right. These intersections eliminate the diverging and merging conflicts; thus, vehicles only fall under crossing conflicts within intersections. However, the traditional way of serving vehicles from one road at a time increases traffic congestion and hinders performance. To address this issue, we extended the synchronous framework for complex intersections with a separate road lane per crossing direction, which was initially presented for single-lane and two-lane intersections in which roads are shared among vehicles with different crossing directions. We compare the performance of our synchronous framework against the traditional Round-Robin (RR) intersection management approach.

2023-07-20Other

Open access

Towards Safe Cooperative Autonomous Platoon systems using COTS Equipment

Publication . Kurunathan, John Harrison; Santos, José; Moreira, Duarte; Santos, Pedro Miguel

The domain of Intelligent Transportation Systems (ITS) is becoming a key candidate to enable safer and efficient mobility in IoT enabled smart cities. Several recent research in cooperative autonomous systems are conducted over simulation frameworks as real experiments are still too costly. In this paper, we present a platooning robotic test-bed platform with a 1/10 scale robotic vehicles that functions based on the input front commercially off the shelf technologies (COTS) such as Lidars and cameras. We also present an in-depth analysis of the functionalities and architecture of the proposed system. We also compare the performance of the aforementioned sensors in some real-life emulated scenarios. From our results, we were able to concur that the camera based platooning is able to perform well at partially observable scenarios than its counterpart.

2023-06-12Journal article

Restricted access

Improved Bus Contention Analysis for 3-Phase Tasks

Publication . Arora, Jatin; Rashid, Syed Aftab; Nelissen, Geoffrey; Maia, Cláudio; Tovar, Eduardo

The 3-phase task execution model has shown to be a good candidate to tackle the memory bus contention problem. It divides the execution of tasks into computation and memory phases that enable a fine-grained memory bus contention analysis. However, existing works that focus on the bus contention analysis for 3-phase tasks, neglect the fact that memory bus contention strongly relates to the number of bus/memory requests generated by tasks, which, in turn, depends on the content of the cache memories during the execution of those tasks. These existing works assume that the worst-case number of bus/memory requests will be generated during all the memory phases of all tasks, irrespective of the already existing content in the cache memory. This overestimates the memory bus contention of tasks, leading to pessimistic worst-case response time (WCRT) bounds. This work proposes a holistic approach towards bus contention analysis for 3-phase tasks by (1) deriving an upper bound on the actual cache misses of tasks that lead to bus/memory requests; (2) improving State-of-the-Art (SoA) bus contention analysis of two bus arbitration schemes that dominate all existing works on the bus contention analysis for 3-phase tasks; and (3) performing an extensive experimental evaluation under different settings to compare the proposed analysis against the SoA. Results show that incorporating a tighter bound on the number of cache misses of tasks into the bus contention analysis can lead to a significant improvement in task set schedulability.

2023-05-30Journal article

Open access

Memory Contention Analysis for 3-Phase Tasks

Publication . Arora, Jatin; Rashid, Syed Aftab; Nelissen, Geoffrey; Maia, Cláudio; Tovar, Eduardo

In multiprocessor-based real-time systems, the main memory is identified as the main source of shared resource contention. Phased execution models such as the 3-phase task execution model has shown to be a good candidate to tackle the memory contention problem. It divides the execution of tasks into computation and memory phases that enable a fine-grained memory contention analysis. However, the existing work that focuses on the memory contention analysis for 3-phase tasks can overestimate the memory contention that can be suffered by the task under analysis due to the write requests. This overestimation can yield pessimistic bounds on the memory access times and memory contention suffered by tasks which in turn lead to pessimistic worst-case response time (WCRT) bounds. Considering the limitation of the state-of-the-art, this work proposes an improved memory contention analysis for the 3-phase task model. Specifically, we propose a memory contention analysis for the 3-phase task model by tightly bounding the memory contention suffered by the task under analysis due to the write requests. The proposed memory contention analysis integrates memory address mapping of tasks to improve the bounds on the maximum memory contention suffered by tasks.

2023-07-07Conference object

Open access

Shared Resource Contention Aware Schedulability Analysis for Multiprocessor Real-Time Systems

Publication . Arora, Jatin; Tovar, Eduardo; Maia, Cláudio

Multicore platforms share the hardware resources such as caches, interconnects, and main memory among all the cores. Due to such sharing, tasks running on different cores compete to access these shared resources which can potentially result in shared resource contention. This shared resource contention can increase the execution times of tasks in a non-deterministic manner. Consequently, the shared resource contention is problematic for hard real-time systems, i.e., systems that run tasks with stringent timing requirements. To address this issue, this PhD dissertation builds novel solutions to model and analyze the shared resource contention that can be suffered by tasks executing on a multicore system. The shared resource contention aware schedulability analysis is then derived by integrating the maximum shared resource contention that can be suffered by the tasks.

2023-04-17Conference object

Open access