Browsing by Issue Date, starting with "2005-06"
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- Efeito do gelo no momento máximo de força durante o movimento concêntrico de extensão do joelhoPublication . Duarte, Raquel; Macedo, RuiA crioterapia é um método comummente usado no tratamento de lesões como coadjuvante na reeducação muscular (JUTTE et al., 2001; OSBAHR et al. 2002; NIEDA, MICHOLOVITZ, 1996; SWENSON et al., 1996). Devido ao efeito analgésico do frio, numa fase sub-aguda, a aplicação crioterápica permite iniciar o exercício mais precocemente (SWENSON et al., 1996; BORGMEYER et al., 2004), todavia, as propriedades termodinâmicas da crioterapia podem afectar a habilidade do músculo gerar tensão (NIEDA, MICHOLOVITZ, 1996).
- Digital Circuit Design Using Dynamic Fitness FunctionsPublication . Reis, Cecília; Tenreiro Machado, J. A.; Cunha, J. BoaventuraThis paper proposes and analyses the performance of a Genetic Algorithm using two new concepts, namely a static fitness function including a discontinuity measure and a fractional-order dynamic fitness function, for the synthesis of combinational logic circuits. In both cases, experiments reveal superior results in terms of speed and convergence to achieve a solution.
- Fractional Dynamic Fitness Functions for GA-based Circuit DesignPublication . Reis, Cecília; Tenreiro Machado, J. A.; Cunha, J. BoaventuraThis paper proposes and analyses the performance of a Genetic Algorithm (GA) using two new concepts, namely a static fitness function including a discontinuity measure and a fractional-order dynamic fitness function. The GA is adopted for the synthesis of combinational logic circuits. In both cases, experiments reveal superior results in terms of speed and convergence to achieve a solution.
- Logic Circuits Synthesis Through Genetic AlgorithmsPublication . Reis, Cecília; Tenreiro Machado, J. A.; Cunha, J. BoaventuraThis paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: the 2-to-1 multiplexer, the one-bit full adder, the four-bit parity checker and the two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of logic gates. It is also studied the scalability problem that emerges from the exponential growth of the truth table when the circuits complexity increases. Furthermore, it is as well investigated the population size and the processing time for achieving a solution in order to establish a compromise between the two parameters.