Browsing by Author "Krug, Margrit R."
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- An Automated Verification Process Based on Scan TechniquePublication . Alves, Gustavo R.; Krug, Margrit R.; Lubaszewski, Marcelo S.; Ferreira, Jose M.Matching the results achieved during circuit simulation with those extracted from circuit functioning is a common verification process. A large number of current verification techniques use the input / output vectors produced during functional simulation as the test vectors applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes a solution for verifying digital designs implemented in currently commercial available CPLDs. All internal flip-flops are included in a scan-chain accessible through the BST infrastructure (using a user-defined optional instruction), while the BS cells are used to apply the input test vectors and capture the circuit responses. These BS cells can either belong to the device-under-test or to other devices, the first controlled through the optional INTEST instruction and the second controlled through the mandatory EXTEST instruction. To speed up the verification process, the test program is automatically generated from information that encompasses the design & development phase.
- From Circuit Simulation to Circuit Verification: An Internal + Boundary Scan-based SolutionPublication . Alves, Gustavo R.; Krug, Margrit R.; Lubaszewski, Marcelo; Ferreira, Jose M.Matching the results obtained from circuit simulation with those extracted from circuit functioning is a common stage of the final verification process. Many current verification techniques use the I/O vectors produced during functional and / or timing simulation, for creating the test vectors to be applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes such a solution for verifying digital designs implemented in currently commercial available CPLDs. The test program is automatically generated from information that encompasses the design & development phase, namely: the file containing the results from simulation, the BSDL file, an internal scan chain description file, and one file containing the user options.
- Implementing a Self- Checking PROFIBUS SlavePublication . Krug, Margrit R.; Lubaszewski, Marcelo S.; Ferreira, Jose M.; Alves, Gustavo R.This work presents the study and preliminary results of the high level implementation of a self-checking Profibus slave. From an existing VHDL description of the device, a test strategy was studied and implemented, so that the whole circuit has embedded test structures capable to perform at-speed test of the slave. In this paper, we show the used test strategies and implementation results achieved from a synthesis process in a FPGA environment.