Browsing by Author "Ferreira, J. M."
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- A Built-In Controller and Extended BS architecture for Prototype Debug and TestPublication . Alves, Gustavo R.; Amaral, Telmo; Ferreira, J. M.Prototype validation is a major concern and hardship in modern electronic products design and development. Simulation, structural test, functional debug, and timing debug are all constituting parts of the validation process, although very often they are addressed as independent and dissociated tasks. In this paper we describe an integrated approach to board-level prototype validation, based on a set of mandatory / optional BST instructions and a built-in controller for debug and test, that addresses the late mentioned tasks as inherent parts of a whole process.
- FPGA Architectures for Reconfigurable ComputingPublication . Gericota, Manuel G.; Alves, Gustavo R.; Ferreira, J. M.To accelerate the execution of an application, repetitive logic and arithmetic computation tasks may be mapped to reconfigurable hardware, since dedicated hardware can deliver much higher speeds than those of a general-purpose processor. However, this is only feasible if the run-time reconfiguration of new tasks is fast enough, so as not to delay application execution. Currently, this is opposed by architectural constraints intrinsic to current Field-Programmable Logic Array (FPGA) architectures. Despite all new features exhibited by current FPGAs, architecturally they are still largely based on general-purpose architectures that are inadequate for the demands of reconfigurable computing. Large configuration file sizes and poor hardware and software support for partial and dynamic reconfiguration limits the acceleration that reconfigurable computing may bring to applications. The objective of this work is the identification of the architectural limitations exhibited by current FPGAs that prevent reconfigurable computing systems to achieve a high efficiency and performance and the proposal of alternatives to its resolution.
- Using the BS register for capturing and storing n-bit sequences in real- timePublication . Alves, Gustavo R.; Ferreira, J. M.Boundary Scan Test is now widely accepted and used for the structural test of Printed Circuit Boards. However, the more demanding requirements of prototype debug and validation are not sufficiently covered by the mandatory and optional operating modes described in the IEEE 1149.1 Standard. Previous work has focused on this problem, having resulted in a new set of user-defined optional instructions addressing the use of the BS register to store in real-time a sequence of contiguous vectors, captured at its parallel inputs without / until / after a certain condition is found. In this paper we describe the tradeoff between input channels and storage capacity, by proposing a new operating mode where the BS register is used to capture / store an n-bit sequence captured at one single functional pin. We also describe how this operating mode can be further extended into the P1149.4 domain, for capturing / storing the n-bit data stream generated by a SD converter placed in the TBIC.