Browsing by Author "Ali Awan, Muhammad"
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- Decoupling Criticality and Importance in Mixed-Criticality SchedulingPublication . Bletsas, Konstantinos; Ali Awan, Muhammad; Souto, Pedro; Åkesson, Benny; Burns, Alan; Tovar, EduardoResearch on mixed-criticality scheduling has flourished since Vestal’s seminal 2007 paper, but more efforts are needed in order to make these results more suitable for industrial adoption and robust and versatile enough to influence the evolution of future certification standards in keeping up with the times. With this in mind, we introduce a more refined task model, in line with the fundamental principles of Vestal’s mode-based adaptive mixed-criticality model, which allows a task’s criticality and its importance to be specified independently from each other. A task’s importance is the criterion that determines its presence in different system modes. Meanwhile, the task’s criticality (reflected in its Safety Integrity Level (SIL) and defining the rules for its software development process), prescribes the degree of conservativeness for the task’s estimated WCET during schedulability testing. We indicate how such a task model can help resolve some of the perceived weaknesses of the Vestal model, in terms of how it is interpreted, and demonstrate how the existing scheduling tests for the classic variant’s of Vestal’s model can be mapped to the new task model essentially without changes.
- Energy-aware Task Allocation onto Unrelated Heterogeneous Multicore Platform for Mixed Criticality SystemsPublication . Ali Awan, Muhammad; Masson, Damien; Tovar, EduardoHeterogeneous multicore platforms have become anattractive choice to deploy mixed criticality systems demandingdiverse computational requirements. One of the major challengesis to efficiently harness the computational power of these multicore platforms while deploying mixed criticality applications.The problem is acerbated with an additional demand of energyefficiency. It is particularly relevant for the battery poweredembedded systems. We propose a partitioning algorithm forunrelated heterogeneous multicore platforms to map mixedcriticality applications that ensures the timeliness property andreduces the energy consumption.
- Memory Bandwidth Regulation for Multiframe Task SetsPublication . Ali Awan, Muhammad; Souto, Pedro; Bletsas, Konstantinos; Åkesson, Benny; Tovar, EduardoTiming analysis of safety-critical real-time embedded systems should be free of both optimistic and pessimistic aspects. The multiframe model was devised to eliminate the pessimism in the schedulability analysis of systems with tasks whose worst-case execution times vary from job to job, according to known patterns. However, this model is optimistic and unsafe for multicores with shared memory controllers, since it ignores memory contention, and existing approaches to stall analysis based on memory regulation are very pessimistic if straightforwardly applied. This paper remedies this by adapting existing stall analyses for memory-regulated systems of conventional Liu-and-Layland tasks to the multiframe model. Experimental evaluations with synthetic task sets (and different task and memory budget assignment heuristics) show up to 85% higher scheduling success ratio for our analysis, compared to the frameagnostic analysis, enabling higher platform utilisation without compromising safety. We also explore implementation aspects, such as how to speed up the analysis and how to trade off accuracy with tractability.
- Mixed-criticality Scheduling with Dynamic Memory Bandwidth RegulationPublication . Ali Awan, Muhammad; Bletsas, Konstantinos; Souto, Pedro; Åkesson, Benny; Tovar, EduardoMixed-criticality multicore system design must often provide both safety guarantees and high performance. Memory bandwidth regulation among different cores can be a useful tool for providing safety guarantees as it mitigates the interference when accessing main memory. The use of mode changes and system models such as those of Vestal can help provide both safety, for critical functions, and scheduling performance, by efficiently utilising the platform. In this work, we therefore combine per-core memory access regulation with the well established Vestal model and improve on the state-of-the-art in two respects. 1) we allow the memory access budgets of the cores to be dynamically adjusted, when the system undergoes a mode change, reflecting the different needs in each mode, for better schedulability. 2) we devise a memory-regulation-aware and stall-aware schedulability analysis for such systems, based on the well-known AMC-max technique. By comparison, the state-of-the-art did not offer the option of dynamic adjustment of core budgets, and only offered regulation-aware schedulability analysis based on AMC-rtb, which is inherently more pessimistic. As an additional contribution, 3) we consider different task assignment and bandwidth allocation heuristics, in experiments with synthetic task sets, to assess the improvement from using dynamic memory budgets and the new analysis. In our results, we have observed an improvement in schedulability ratio up to 9.1% over the state-of-the-art algorithm.
- Mixed-criticality Scheduling with Memory Bandwidth RegulationPublication . Ali Awan, Muhammad; Souto, Pedro; Bletsas, Konstantinos; Åkesson, Benny; Tovar, EduardoMixed-criticality (MC) multicore system design must reconcile safety guarantees and high performance. The interference among cores on shared resources in such systems leads to unpredictable temporal behaviour. Memory bandwidth regulation among different cores can be a useful tool to mitigate the interference when accessing main memory. However, for mixed-criticality systems conforming to the (well-established) Vestal model, the existing schedulability analyses are oblivious to memory stalling effects, including stalls from memory bandwidth regulation. This makes it unsafe. In this paper, we address this issue by formulating a schedulability analysis for mixed-criticality fixed-priority-scheduled multicore systems using per-core memory access regulation. We also propose multiple heuristics for memory bandwidth allocation and task-to-core assignment. We implement our analysis and heuristics in a tool and evaluate them, performance-wise, through extensive experiments. Our experiments show that stall-oblivious schedulability analysis may be optimistic due to contention on shared memory resources.
- Response time analysis of multiframe mixed-criticality systemsPublication . Hussain, Ishfaq; Ali Awan, Muhammad; Souto, Pedro; Bletsas, Konstantinos; Åkesson, Benny; Tovar, EduardoThe well-known model of Vestal aims to avoid excessive pessimism in the quantification of the processing requirements of mixedcriticality systems, while still guaranteeing the timeliness of highercriticality functions. This can bring important savings in system costs, and indirectly help meet size, weight and power constraints. This efficiency is promoted via the use of multiple worst-case execution time (WCET) estimates for the same task, with each such estimate characterised by a confidence associated with a different criticality level. However, even this approach can be very pessimistic when the WCET of successive instances of the same task can vary greatly according to a known pattern, as in MP3 and MPEG codecs or the processing of ADVB video streams. In this paper, we present a schedulability analysis for the multiframe mixed-criticality model, which allows tasks to have multiple, periodically repeating, WCETs in the same mode of operation. Our work extends both the analysis techniques for Static Mixed-Cricality scheduling (SMC) and Adaptive Mixed-Criticality scheduling (AMC), on one hand, and the schedulability analysis for multiframe task systems on the other. Our proposed worst-case response time (WCRT) analysis for multiframe mixed-criticality systems is considerably less pessimistic than applying the SMC, AMC-rtb and AMC-max tests obliviously to the WCET variation patterns. Experimental evaluation with synthetic task sets demonstrates up to 63.8% higher scheduling success ratio (in absolute terms) compared to the best of the frame-oblivious tests
- Techniques and Analysis for Mixed-criticality Scheduling with Mode-dependent Server Execution BudgetsPublication . Ali Awan, Muhammad; Bletsas, Konstantinos; Souto, Pedro F.; Åkesson, Benny; Tovar, EduardoIn mixed-criticality systems, tasks of different criticality share system resources, mainly to reduce cost. Cost is further reduced by using adaptive mode-based scheduling arrangements, such as Vestal’s model, to improve resource efficiency, while guaranteeing schedulability of critical functionality. To simplify safety certification, servers are often used to provide temporal isolation between tasks. In its simplest form, a server is a periodically recurring time window, in which some tasks are scheduled. A server’s computational requirements may greatly vary in different modes, although state-of-the-art techniques and schedulability tests do not allow different budgets to be used by a server in different modes. This results in a single conservative execution budget for all modes, increasing system cost. The goal of this paper is to reduce the cost of mixed-criticality systems through three main contributions: (i) a scheduling arrangement for uniprocessor systems employing fixed-priority scheduling within periodic servers, whose budgets are dynamically adjusted at run-time in the event of a mode change, (ii) a new schedulability analysis for such systems, and (iii) heuristic algorithms for assigning budgets to servers in different modes and ordering the execution of the servers. Experiments with synthetic task sets demonstrate considerable improvements (up to 52.8%) in
- Towards the Certification of Multicore Platforms in the Avionics DomainPublication . Ali Awan, Muhammad; Meumeu Yomsi, Patrick; Bletsas, Konstantinos; Nélis, Vincent; Tovar, Eduardo; Souto, PedroIn the last decade, the semiconductor industry has experienced a paradigm shift from single core design to a multicore architecture era. This trend is driven by the fact that the increase in clock speed to enhance the performance of a core has hit a limit as the performance per watt became costly at high frequencies. A multicore processor (MCP) combines two or more cores into a single package (single or multiple dies) such that they can execute programs simultaneously. Although this feature is very appealing, it comes with new challenges, unfortunately. Most MCP platforms present many sources of unpredictability as the large majority of hardware vendors are mainly interested by improving the average performance of the system. This work discusses some sources of non-determinism and highlights the envisioned methodology to mitigate or eliminate their effect in the context of safety critical systems.
- Worst-case Stall Analysis for Multicore Architectures with Two Memory ControllersPublication . Ali Awan, Muhammad; Souto, Pedro F.; Bletsas, Konstantinos; Åkesson, Benny; Tovar, EduardoIn multicore architectures, there is potential for contention between cores when accessing shared resources, such as system memory. Such contention scenarios are challenging to accurately analyse, from a worst-case timing perspective. One way of making memory contention in multicores more amenable to timing analysis is the use of memory regulation mechanisms. It restricts the number of accesses performed by any given core over time by using periodically replenished per-core budgets. Typically, this assumes that all cores access memory via a single shared memory controller. However, ever-increasing bandwidth requirements have brought about architectures with multiple memory controllers. These control accesses to different memory regions and are potentially shared among all cores. While this presents an opportunity to satisfy bandwidth requirements, existing analysis designed for a single memory controller are no longer safe. This work formulates a worst-case memory stall analysis for a memory-regulated multicore with two memory controllers. This stall analysis can be integrated into the schedulability analysis of systems under fixed-priority partitioned scheduling. Five heuristics for assigning tasks and memory budgets to cores in a stall-cognisant manner are also proposed. We experimentally quantify the cost in terms of extra stall for letting all cores benefit from the memory space offered by both controllers, and also evaluate the five heuristics for different system characteristics.