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A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling

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dc.contributor.authorCasini, Daniel
dc.contributor.authorBiondi, Alessandro
dc.contributor.authorNelissen, Geoffrey
dc.contributor.authorButtazzo, Giorgio
dc.date.accessioned2020-10-21T10:47:55Z
dc.date.embargo2120
dc.date.issued2020
dc.description.abstractWhen adopting multi-core systems for safety-critical applications, certification requirements mandate bounding the delays incurred in accessing shared resources. This is the case of global memories, whose access is often regulated by memory controllers optimized for average-case performance and not designed to be predictable. As a consequence, worst-case bounds on memory access delays often result to be too pessimistic, drastically reducing the advantage of having multiple cores. This paper proposes a fine-grained analysis of the memory contention experienced by parallel tasks running on a multi-core platform. To this end, an optimization problem is formulated to bound the memory interference by leveraging a three-phase execution model and holistically considering multiple memory transactions issued during each phase. Experimental results show the advantage in adopting the proposed approach on both synthetic task sets and benchmarks.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.doi10.1109/RTAS48715.2020.000-3pt_PT
dc.identifier.issn2642-7346
dc.identifier.urihttp://hdl.handle.net/10400.22/16343
dc.language.isoengpt_PT
dc.peerreviewedyespt_PT
dc.publisherIEEEpt_PT
dc.relationPReFECT, ref. POCI-01-0145-FEDER-029119pt_PT
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/9113115pt_PT
dc.subjectMultiprocessing programspt_PT
dc.subjectOptimisationpt_PT
dc.subjectParallel processingpt_PT
dc.subjectProcessor schedulingpt_PT
dc.subjectSafety-critical softwarept_PT
dc.subjectStorage managementpt_PT
dc.titleA Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Schedulingpt_PT
dc.typeconference object
dspace.entity.typePublication
oaire.citation.conferencePlaceOnlinept_PT
oaire.citation.endPage252pt_PT
oaire.citation.startPage239pt_PT
oaire.citation.titleProceedings of the 26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2020)pt_PT
person.familyNameNelissen
person.givenNameGeoffrey
person.identifier.ciencia-idE51E-C723-0D77
person.identifier.orcid0000-0003-4141-6718
person.identifier.scopus-author-id41561808600
rcaap.rightsclosedAccesspt_PT
rcaap.typeconferenceObjectpt_PT
relation.isAuthorOfPublicatione23673cc-6b82-4d9c-94fb-4b4fca051b0d
relation.isAuthorOfPublication.latestForDiscoverye23673cc-6b82-4d9c-94fb-4b4fca051b0d

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