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TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs

2015-05-23Journal article Restricted access
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dc.contributor.authorJafri, Syed M.A.H.
dc.contributor.authorDaneshtalab, Masoud
dc.contributor.authorHemani, Ahmed
dc.contributor.authorAwan, Muhammad Ali
dc.contributor.authorPlosila, Juha
dc.date.accessioned2015-10-16T11:11:57Z
dc.date.available2015-10-16T11:11:57Z
dc.date.issued2015-05-23
dc.description.abstractCoarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications (e.g. 4G, CDMA, etc.). Recently proposed CGRAs offer time-multiplexing and dynamic applications parallelism to enhance device utilization and reduce energy consumption at the cost of additional memory (up to 50% area of the overall platform). To reduce the memory overheads, novel CGRAs employ either statistical compression, intermediate compact representation, or multicasting. Each compaction technique has different properties (i.e. compression ratio, decompression time and decompression energy) and is best suited for a particular class of applications. However, existing research only deals with these methods separately. Moreover, they only analyze the compaction ratio and do not evaluate the associated energy overheads. To tackle these issues, we propose a polymorphic compression architecture that interleaves these techniques in a unique platform. The proposed architecture allows each application to take advantage of a separate compression/decompression hierarchy (consisting of various types and implementations of hardware/software decoders) tailored to its needs. Simulation results, using different applications (FFT, Matrix multiplication, and WLAN), reveal that the choice of compression hierarchy has a significant impact on compression ratio (up to 52%), decompression energy (up to 4 orders of magnitude), and configuration time (from 33 n to 1.5 s) for the tested applications. Synthesis results reveal that introducing adaptivity incurs negligible additional overheads (1%) compared to the overall platform area.pt_PT
dc.identifier.doi10.1016/j.micpro.2015.05.002
dc.identifier.urihttp://hdl.handle.net/10400.22/6713
dc.language.isoengpt_PT
dc.peerreviewedyespt_PT
dc.publisherElsevierpt_PT
dc.relationUID/CEC/04234/2013 (CISTER Research Centre)pt_PT
dc.relationARTEMIS/0001/2013 – JU Grant Nr. 621429 (EMC2)pt_PT
dc.relationNORTE-07-0124-FEDER-000063 (BEST-CASE, New Frontiers)pt_PT
dc.relation.ispartofseriesMicroprocessors and Microsystems;
dc.relation.publisherversionhttp://www.sciencedirect.com/science/article/pii/S014193311500054Xpt_PT
dc.subjectReconfigurable architecturespt_PT
dc.subjectCGRA configurationpt_PT
dc.subjectCoarse grained reconfigurable architecturespt_PT
dc.subjectCompression/decompression hierarchypt_PT
dc.subjectAdaptive systemspt_PT
dc.subjectCompressionpt_PT
dc.titleTEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAspt_PT
dc.typejournal article
dspace.entity.typePublication
oaire.citation.titleMicroprocessors and Microsystemspt_PT
rcaap.rightsopenAccesspt_PT
rcaap.typearticlept_PT

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