Publication
Logic-based schedulability analysis for compositional hard real-time embedded systems
| dc.contributor.author | Pedro, André | |
| dc.contributor.author | Pereira, David | |
| dc.contributor.author | Pinho, Luís Miguel | |
| dc.contributor.author | Pinto, Jorge Sousa | |
| dc.date.accessioned | 2015-11-04T15:21:58Z | |
| dc.date.available | 2015-11-04T15:21:58Z | |
| dc.date.issued | 2015-02 | |
| dc.description.abstract | Over the past decades several approaches for schedulability analysis have been proposed for both uni-processor and multi-processor real-time systems. Although different techniques are employed, very little has been put forward in using formal specifications, with the consequent possibility for mis-interpretations or ambiguities in the problem statement. Using a logic based approach to schedulability analysis in the design of hard real-time systems eases the synthesis of correct-by-construction procedures for both static and dynamic verification processes. In this paper we propose a novel approach to schedulability analysis based on a timed temporal logic with time durations. Our approach subsumes classical methods for uni-processor scheduling analysis over compositional resource models by providing the developer with counter-examples, and by ruling out schedules that cause unsafe violations on the system. We also provide an example showing the effectiveness of our proposal. | pt_PT |
| dc.identifier.doi | 10.1145/2752801.2752808 | |
| dc.identifier.uri | http://hdl.handle.net/10400.22/6816 | |
| dc.language.iso | eng | pt_PT |
| dc.peerreviewed | yes | pt_PT |
| dc.publisher | ACM | pt_PT |
| dc.relation | FCOMP-01-0124-FEDER-022701 (CISTER) | pt_PT |
| dc.relation | FCOMP- 01-0124-FEDER-015006 (VIPCORE) | pt_PT |
| dc.relation | FCOMP-01-0124- FEDER-020486 (AVIACC) | pt_PT |
| dc.relation.ispartofseries | ACM SIGBED Review;Vol. 12, Issue 1 | |
| dc.relation.publisherversion | http://dl.acm.org/citation.cfm?doid=2752801.2752808 | pt_PT |
| dc.subject | Temporal logic | pt_PT |
| dc.subject | Schedulability analysis | pt_PT |
| dc.subject | Compositional | pt_PT |
| dc.subject | Hard Real-Time Systems | pt_PT |
| dc.subject | Embedded Systems | pt_PT |
| dc.title | Logic-based schedulability analysis for compositional hard real-time embedded systems | pt_PT |
| dc.type | journal article | |
| dspace.entity.type | Publication | |
| oaire.citation.endPage | 64 | pt_PT |
| oaire.citation.issue | 1 | pt_PT |
| oaire.citation.startPage | 56 | pt_PT |
| oaire.citation.title | ACM SIGBED Review - Special Issue on the 6th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems | pt_PT |
| oaire.citation.volume | 12 | pt_PT |
| person.familyName | Pinho | |
| person.givenName | Luis Miguel | |
| person.identifier.ciencia-id | 8112-2108-F3B2 | |
| person.identifier.orcid | 0000-0001-6888-1340 | |
| person.identifier.rid | M-3416-2013 | |
| person.identifier.scopus-author-id | 6602594556 | |
| rcaap.rights | openAccess | pt_PT |
| rcaap.type | article | pt_PT |
| relation.isAuthorOfPublication | fd791145-af93-47d9-bbe8-647a326d2f39 | |
| relation.isAuthorOfPublication.latestForDiscovery | fd791145-af93-47d9-bbe8-647a326d2f39 |