Publication
HopliteRT*: Real-Time NoC for FPGA
| dc.contributor.author | Ribot González, Yilian | |
| dc.contributor.author | Nelissen, Geoffrey | |
| dc.date.accessioned | 2020-11-04T15:01:34Z | |
| dc.date.embargo | 2120 | |
| dc.date.issued | 2020 | |
| dc.description | This article was presented in part at the International Conference on Embedded Software 2020 and appears as part of the ESWEEK-TCAD special issue. | pt_PT |
| dc.description.abstract | With the increasing number of computation nodes integrated in multi and many-core platforms, network-on-chips (NoCs) emerged as a new communication medium in systems-on-chips (SoCs). HopliteRT is a new NoC design that was recently proposed to address the needs of real-time systems whilst respecting the constraints of field-programmable gate array (FPGA) platforms. In this article, we: 1) introduce priority-based routing in HopliteRT; 2) change the network topology in order to improve the packets’ worst-case traversal time (WCTT); 3) identify a flaw in the existing timing analysis of HopliteRT; and 4) develop a new timing analysis that is proven correct. We also show by means of experiments that the modifications of HopliteRT proposed in this article allows for at least 2× improvement on the worst and average case traversal time of high priority packets, without impacting the quality of service of low-priority packets. The timing properties of high priority flows are greatly improved for negligible additional hardware costs. The proposed NoC has been implemented in Verilog and synthesized for a Xilinx Virtex-7 FPGA platform. | pt_PT |
| dc.description.version | info:eu-repo/semantics/publishedVersion | pt_PT |
| dc.identifier.doi | 10.1109/TCAD.2020.3012748 | pt_PT |
| dc.identifier.issn | 0278-0070 | |
| dc.identifier.uri | http://hdl.handle.net/10400.22/16428 | |
| dc.language.iso | eng | pt_PT |
| dc.peerreviewed | yes | pt_PT |
| dc.publisher | Institute of Electrical and Electronics Engineers | pt_PT |
| dc.relation.publisherversion | https://ieeexplore.ieee.org/document/9211415 | pt_PT |
| dc.subject | Field programmable gate array | pt_PT |
| dc.subject | Network-onchips | pt_PT |
| dc.subject | Real-time embedded systems | pt_PT |
| dc.subject | Systems-on-chips | pt_PT |
| dc.subject | Timing analysis | pt_PT |
| dc.title | HopliteRT*: Real-Time NoC for FPGA | pt_PT |
| dc.type | journal article | |
| dspace.entity.type | Publication | |
| oaire.citation.endPage | 3661 | pt_PT |
| oaire.citation.issue | 11 | pt_PT |
| oaire.citation.startPage | 3650 | pt_PT |
| oaire.citation.title | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | pt_PT |
| oaire.citation.volume | 39 | pt_PT |
| person.familyName | Ribot González | |
| person.familyName | Nelissen | |
| person.givenName | Yilian | |
| person.givenName | Geoffrey | |
| person.identifier.ciencia-id | E51E-C723-0D77 | |
| person.identifier.orcid | 0000-0002-4089-7794 | |
| person.identifier.orcid | 0000-0003-4141-6718 | |
| person.identifier.scopus-author-id | 41561808600 | |
| rcaap.rights | closedAccess | pt_PT |
| rcaap.type | article | pt_PT |
| relation.isAuthorOfPublication | 2738baf6-1d5f-44db-b199-75789aa83529 | |
| relation.isAuthorOfPublication | e23673cc-6b82-4d9c-94fb-4b4fca051b0d | |
| relation.isAuthorOfPublication.latestForDiscovery | e23673cc-6b82-4d9c-94fb-4b4fca051b0d |
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