Publication
Analyzing Fixed Task Priority Based Memory Centric Scheduler for the 3-Phase Task Model
dc.contributor.author | Arora, Jatin | |
dc.contributor.author | Rashid, Syed Aftab | |
dc.contributor.author | Maia, Cláudio | |
dc.contributor.author | Tovar, Eduardo | |
dc.date.accessioned | 2022-10-03T15:42:55Z | |
dc.date.available | 2022-10-03T15:42:55Z | |
dc.date.issued | 2022-08-23 | |
dc.description.abstract | The sharing of main memory among concurrently executing tasks on a multicore platform results in increasing the execution times of those tasks in a non-deterministic manner. The use of phased execution models that divide the execution of tasks into distinct memory and execution phase(s), e.g., the PRedictable Execution Model (PREM) and the 3-Phase task model, along with Memory Centric Scheduling (MCS) present a promising solution to reduce main memory interference among tasks. Existing works in the state-of-the-art that focus on MCS have considered (i) a TDMA based memory scheduler, i.e., tasks' memory requests are served under a static TDMA schedule, and (ii) Processor-Priority (PP) based memory scheduler, i.e., tasks' memory requests are served depending on the priority of the processor/core on which the task is executing. This paper extends MCS by considering a Task-Priority (TP) based memory scheduler, i.e., tasks' memory requests are served under a global priority order depending on the priority of the task that issues the requests. We present an analysis to bound the total memory interference that can be suffered by the tasks under the TP-based MCS. In contrast to most existing works on MCS that consider non-preemptive tasks, our analysis considers limited preemptive scheduling. Additionally, we investigate the impact of different preemption points on the memory interference of tasks. Experimental results show that our proposed TP-based MCS can significantly reduce memory interference that can be suffered by the tasks in comparison to the PP-based MCS approach. | pt_PT |
dc.description.sponsorship | This work was partially supported by European Union’s Horizon 2020 -The EU Framework Programme for Research and Innovation 2014-2020, under grant agreement No. 732505. Project ”TEC4Growth - Pervasive Intelligence, Enhancers and Proofs of Concept with Industrial Impact/NORTE-01-0145-FEDER000020” financed by the North Portugal Regional Operational Programme (NORTE 2020), under the PORTUGAL 2020 Partnership Agreement; also by National Funds through FCT/MCTES (Portuguese Foundation for Science and Technology), within the CISTER Research Unit (UIDP/UIDB/04234/2020); by FCT and the Portuguese National Innovation Agency (ANI), under the CMU Portugal partnership, through the European Regional Development Fund (ERDF) of the Operational Competitiveness Programme and Internationalization (COMPETE 2020), under the PT2020 Partnership Agreement, within project FLOYD (POCI-01-0247-FEDER-045912), also by FCT under PhD grant 2020.09532.BD. | pt_PT |
dc.description.version | info:eu-repo/semantics/publishedVersion | pt_PT |
dc.identifier.uri | http://hdl.handle.net/10400.22/20907 | |
dc.language.iso | eng | pt_PT |
dc.relation | NORTE-01-0145-FEDER000020 | pt_PT |
dc.relation | Lightweight Computation for Networks at the Edge | |
dc.relation | POCI-01-0247-FEDER-045912 | pt_PT |
dc.relation | Bus-Aware Schedulability Analysis in Multiprocessor Real-Time Systems | |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | pt_PT |
dc.title | Analyzing Fixed Task Priority Based Memory Centric Scheduler for the 3-Phase Task Model | pt_PT |
dc.title.alternative | 220608 | pt_PT |
dc.type | journal article | |
dspace.entity.type | Publication | |
oaire.awardTitle | Lightweight Computation for Networks at the Edge | |
oaire.awardTitle | Bus-Aware Schedulability Analysis in Multiprocessor Real-Time Systems | |
oaire.awardURI | info:eu-repo/grantAgreement/EC/H2020/732505/EU | |
oaire.awardURI | info:eu-repo/grantAgreement/FCT/POR_NORTE/2020.09532.BD/PT | |
oaire.citation.conferencePlace | Taipei, Taiwan | pt_PT |
oaire.citation.title | IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Technical Session. | pt_PT |
oaire.fundingStream | H2020 | |
oaire.fundingStream | POR_NORTE | |
person.familyName | Arora | |
person.familyName | Maia | |
person.familyName | Tovar | |
person.givenName | Jatin | |
person.givenName | Cláudio Roberto Ribeiro | |
person.givenName | Eduardo | |
person.identifier.ciencia-id | 8816-61C3-8763 | |
person.identifier.ciencia-id | EC13-23BF-2018 | |
person.identifier.ciencia-id | 6017-8881-11E8 | |
person.identifier.orcid | 0000-0001-6198-6852 | |
person.identifier.orcid | 0000-0002-6567-4271 | |
person.identifier.orcid | 0000-0001-8979-3876 | |
person.identifier.scopus-author-id | 7006312557 | |
project.funder.identifier | http://doi.org/10.13039/501100008530 | |
project.funder.identifier | http://doi.org/10.13039/501100001871 | |
project.funder.name | European Commission | |
project.funder.name | Fundação para a Ciência e a Tecnologia | |
rcaap.rights | openAccess | pt_PT |
rcaap.type | article | pt_PT |
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