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A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

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dc.contributor.authorFidalgo, André Vaz
dc.contributor.authorAlves, Gustavo R.
dc.contributor.authorGericota, Manuel G.
dc.contributor.authorFerreira, José M.
dc.date.accessioned2014-03-27T10:52:46Z
dc.date.available2014-03-27T10:52:46Z
dc.date.issued2008
dc.description.abstractOn-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.por
dc.identifier.doi10.1145/1404371.1404388
dc.identifier.isbn978-1-60558-231-3
dc.identifier.urihttp://hdl.handle.net/10400.22/4254
dc.language.isoengpor
dc.peerreviewedyespor
dc.publisherACMpor
dc.relation.ispartofseriesSBCCI'2008
dc.relation.publisherversionhttp://dl.acm.org/citation.cfm?doid=1404371.1404388por
dc.subjectDependabilitypor
dc.subjectFault injectionpor
dc.subjectReal-time systemspor
dc.titleA comparative analysis of fault injection methods via enhanced on-chip debug infrastructurespor
dc.typeconference object
dspace.entity.typePublication
oaire.citation.endPage27por
oaire.citation.startPage22por
oaire.citation.titleProceedings of the 21st annual symposium on Integrated circuits and system designpor
person.familyNameFidalgo
person.familyNameAlves
person.familyNameGericota
person.givenNameAndré
person.givenNameGustavo
person.givenNameManuel
person.identifierR-001-F04
person.identifier150015
person.identifier.ciencia-idC91D-EF99-47D9
person.identifier.ciencia-id4210-4DF2-5206
person.identifier.ciencia-idCE13-92FF-2097
person.identifier.orcid0000-0003-1219-3105
person.identifier.orcid0000-0002-1244-8502
person.identifier.orcid0000-0001-9774-816X
person.identifier.ridR-7611-2016
person.identifier.ridI-7876-2014
person.identifier.scopus-author-id15922707800
person.identifier.scopus-author-id7006053908
rcaap.rightsopenAccesspor
rcaap.typeconferenceObjectpor
relation.isAuthorOfPublication17a751b2-e87b-497b-b06c-9d4c6c88a4bb
relation.isAuthorOfPublication01800568-7eaf-41d9-b78d-cf64f7c7381d
relation.isAuthorOfPublicationc84c77d9-ad89-48d1-9901-de8d5f7300b5
relation.isAuthorOfPublication.latestForDiscoveryc84c77d9-ad89-48d1-9901-de8d5f7300b5

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