Repository logo
 
Publication

Schedulability Analysis for 3-Phase Tasks with Partitioned Fixed-Priority Scheduling

2022-08-16Journal article Open access
Simple item page
dc.contributor.authorArora, Jatin
dc.contributor.authorMaia, Cláudio
dc.contributor.authorRashid, Syed Aftab
dc.contributor.authorNelissen, Geoffrey
dc.contributor.authorTovar, Eduardo
dc.date.accessioned2022-09-20T14:17:03Z
dc.date.available2022-09-20T14:17:03Z
dc.date.issued2022-08-16
dc.description.abstractMulticore platforms are being increasingly adopted in Cyber-Physical Systems (CPS) due to their advantages over single-core processors, such as raw computing power and energy efficiency. Typically, multicore platforms use a shared memory bus that connects the cores to the off-chip main memory. This sharing of memory bus may cause tasks running on different cores to compete for access to the main memory whenever data/instructions are need to be read/written from/to the main memory. Such competition is problematic, as it may cause variations in the execution time of tasks in a non-deterministic way. To reduce the complexity of analysing this problem, the 3-phase task model was proposed that divides tasks' executions into distinct memory and execution phases. The distinctive memory phases are then scheduled to eliminate/minimize main memory contention between concurrently executing tasks. However, 3-phase tasks running on different cores may still compete to access the shared memory bus/main memory in order to execute memory phases. This paper presents a partitioned scheduling-based approach that allows one to derive memory bus contention-aware worst-case response time of tasks that follow the 3-phase task model. In particular, the bus-contention analysis is derived by considering two memory access models, i.e., (i) dedicated memory access model, where a core having allowed to access the main memory via memory bus is permitted to execute more than one memory phase, and (ii) fair memory access model, that restrict each core to execute only one memory phase in its allocated bus access. Both these models represent different system and application requirements, and the resulting bus contention of tasks may vary depending on the considered model. To evaluate the effectiveness of the proposed bus contention analysis, we compare its performance against an existing analysis in the state-of-the-art by performing (i) case-study experiments, using benchmarks from the Mälardalen Benchmark suite, and (ii) empirical evaluation using synthetic task sets. Results show that our proposed analysis can improve task set schedulability of 3-phase tasks by up to 88 percentage points.pt_PT
dc.description.sponsorshipThis work was partially supported by European Union’s Horizon 2020 -The EU Framework Programme for Research and Innovation 2014-2020, under grant agreement No. 732505. Project “TEC4Growth - Pervasive Intelligence, Enhancers and Proofs of Concept with Industrial Impact/NORTE-01-0145-FEDER000020” 845 financed by the North Portugal Regional Operational Programme (NORTE 2020), under the PORTUGAL 2020 Partnership Agreement; also by National Funds through FCT/MCTES (Portuguese Foundation for Science and Technology), within the CISTER Research Unit (UIDP/UIDB/04234/2020); by FCT and the Portuguese National Innovation Agency (ANI), under the CMU Portugal partnership, through the European Regional Development Fund (ERDF) of the Operational Competitiveness Programme and Internationaliza850 tion (COMPETE 2020), under the PT2020 Partnership Agreement, within project FLOYD (POCI-01-0247- FEDER-045912), also by FCT under PhD grant 2020.09532.BD.
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.urihttp://hdl.handle.net/10400.22/20890
dc.language.isoengpt_PT
dc.relationNORTE-01-0145-FEDER000020
dc.relationPOCI-01-0247-FEDER-045912
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/pt_PT
dc.subjectReal-Time Systemspt_PT
dc.subjectMulticore Processorspt_PT
dc.subjectPartitioned Schedulingpt_PT
dc.subjectBus Contentionpt_PT
dc.subjectSchedulability Analysispt_PT
dc.titleSchedulability Analysis for 3-Phase Tasks with Partitioned Fixed-Priority Schedulingpt_PT
dc.title.alternative220801pt_PT
dc.typejournal article
dspace.entity.typePublication
person.familyNameArora
person.familyNameMaia
person.familyNameNelissen
person.familyNameTovar
person.givenNameJatin
person.givenNameCláudio Roberto Ribeiro
person.givenNameGeoffrey
person.givenNameEduardo
person.identifier.ciencia-id8816-61C3-8763
person.identifier.ciencia-idEC13-23BF-2018
person.identifier.ciencia-idE51E-C723-0D77
person.identifier.ciencia-id6017-8881-11E8
person.identifier.orcid0000-0001-6198-6852
person.identifier.orcid0000-0002-6567-4271
person.identifier.orcid0000-0003-4141-6718
person.identifier.orcid0000-0001-8979-3876
person.identifier.scopus-author-id41561808600
person.identifier.scopus-author-id7006312557
rcaap.rightsopenAccesspt_PT
rcaap.typearticlept_PT
relation.isAuthorOfPublication21bbedd3-1ba1-40a2-9ceb-42bbfd0abbee
relation.isAuthorOfPublication382626bf-f6e8-427b-b5fa-e470b5b0fb03
relation.isAuthorOfPublicatione23673cc-6b82-4d9c-94fb-4b4fca051b0d
relation.isAuthorOfPublication80b63d8a-2e6d-484e-af3c-55849d0cb65e
relation.isAuthorOfPublication.latestForDiscovery80b63d8a-2e6d-484e-af3c-55849d0cb65e

Files

Original bundle
Now showing 1 - 1 of 1
No Thumbnail Available
Name:
ART_CISTER-TR-220801.pdf
Size:
1.12 MB
Format:
Adobe Portable Document Format
Download
License bundle
Now showing 1 - 1 of 1
No Thumbnail Available
Name:
license.txt
Size:
1.71 KB
Format:
Item-specific license agreed upon to submission
Description:
Download

Collections

ISEP – CISTER – Artigos